• The Journal of the Korea Contents Association
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• v.7 no.8
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• pp.41-49
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• 2007

BCI system integrates control or telecommunication system with generating electric signals in scalp itself after signal acquisition. This system detect a movement of EEG at real time, can control an electron equipment using a generated signal through EEG movement or software-based processor. In this paper, we deal with removing and separating artifacts induceced from measurement when brain-computer interface system that analyzes recognizes EEG signals occurred from various mental states. In this paper, we proposed a method of EEG classification and an artifact interval detection using bisection mathematical modeling in the EEG classification process for BCI system implementation.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.4
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• pp.437-446
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• 2018

This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{\mu}s$ with a vector of length 48 with 2 non-zero elements.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1565-1575
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• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1601-1614
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• 1997

In this paper, We suggest a technique for delivering frame(CM transfering unit) based CM data streams from MOD servers to clients on ATM-LAN environment. The term 'frame' indicates the CM transferring unit. In detail, each clients try to adapt native ATM-specific service which can be connected directly from application layer to AAL without convening transport and IP layer. Also, we suggest and show result of implementation about transparent browsing mechanism using navigation server, session setting procedures using PVC between server and clients, application, AAL and QoS negotiation and reservation procedure, splitting and reassembling algorithm for frames over MTU size.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.653-657
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• 2000

The paper describes the contents and results of the national project named "Development of Computer Integrated Product Design for Automation Equipment". It is focussed on the real-time control '||'&'||' monitoring of manufacturing process for automobile rubber parts. Automobile rubber parts industy is one of the typical process that high11 depends upon manufacturing facilities and equipments. So. it requires high cost and engineering technolog) on plant implementation. But most companies of rubber parts industries are small or mid companies that habe weak abilities for plant implementation properly and systematically. Therefore, for upgrading the levelof automation. it is necessar). to dekelope the computer based management and monitoring slsteni that enables to build-up the common base of automation and systemization. 'Through this project. we developed low cost real-time monitoring system for banbun mixing process '||'&'||' mold injection process of rubbcr parts manufacturing, that is composed with DDCU(Distributed Digital Control Unit),signal interfaces to gathering mon~toring terms and speciall\ developed functional sofhare including some algorithm for management '||'&'||' process monitoring

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.179-186
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• 2009

This paper describes the design and implementation for spread spectrum FTS encoder and decoder. The FTS command format is defined by 64 bit encrypted packet that contains all required information relayed between the ground and the vehicle. Encryption is accomplished using the Tripple-DES encryption algorithm in block encryption form. The proposed FTS encoder and decoder is using the Convolution Encoding and Viterbi Decoding for forward error correction. The Spread Spectrum Modulation is done using a PN code, which is 256 bit gold code. The simulation result shows that the designed FTS decoder is compatible with the designed FTS encoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.978-985
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• 2003

The implementation of abnormal behavior detection IDS is more difficult than the implementation of misuse behavior detection IDS because usage patterns are various. Therefore, most of commercial IDS is misuse behavior detection IDS. However, misuse behavior detection IDS cannot detect system intrusion in case of modified intrusion patterns occurs. In this paper, we apply data mining so as to detect intrusion with only audit data related in intrusion among many audit data. The agent in the distributed IDS can collect log data as well as monitoring target system. False positive should be minimized in order to make detection accuracy high, that is, core of intrusion detection system. So We apply data mining algorithm for prediction of modified intrusion pattern in the level of audit data learning.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.53-58
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• 2014

As the amount of data between ECUs has increased, the FlexRay consortium proposed FlexRay network system which has larger bandwidth than CAN. But because of implementation cost, CAN and FlexRay hybrid network with FlexRay-CAN gateway will make up the largest part of in-vehicle networks for the present. In this paper, a FlexRay-CAN gateway for a real time feedback control system is implemented, and a data packing algorithm is presented. Finally, a real control experiment with multi-motor system is conducted to verify the proposed gateway system.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.6
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.