• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.2
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• pp.209-214
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• 2018

The subway, which is an urban railway, is the core of public transportation. Urban railways are always exposed to serious problems such as theft, crime and terrorism, as many passengers use them. Especially, due to the nature of urban railway environment, the scope of surveillance is widely dispersed and the range of surveillance target is rapidly increasing. Therefore, it is difficult to perform comprehensive management by passive surveillance like existing CCTV. In this paper, we propose the implementation, design method and object recognition algorithm for intelligent object recognition system in urban railway. The object recognition system that we propose is to analyze the camera images in the history and to recognize the situations where there are objects in the landing area and the waiting area that are not moving for more than a certain time. The proposed algorithm proved its effectiveness by showing detection rate of 100% for Selected area detection, 82% for detection in neglected object, and 94% for motionless object detection, compared with 84.62% object recognition rate using existing Kalman filter.

• The KIPS Transactions:PartC
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• v.15C no.2
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• pp.133-140
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• 2008

In this paper, we propose a high performance elliptic curve cryptographic processor over $GF(2^{163})$. The proposed architecture is based on a modified Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for $GF(2^{163})$ field arithmetic. To achieve a high throughput rates, we design two new word-level arithmetic units over $GF(2^{163})$ and derive a parallelized elliptic curve point doubling and point addition algorithm with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with 2 times increased hardware complexity compared with the previous hardware implementation proposed by Shu. et. al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.3
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• pp.273-278
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• 2004

In this paper, the recurrent neural networks (RNN) is applied to compensate for HMM recognition algorithm, which is commonly used as main recognizer. Among these recurrent neural networks, the multi-layer recurrent neural prediction model (MRNPM), which allows operating in real-time, is used to implement learning and recognition, and HMM and MRNPM are used to design a hybrid-type main recognizer. After testing the designed speech recognition algorithm with Korean number pronunciations (13 words), which are hardly distinct, for its speech-independent recognition ratio, about 5% improvement was obtained comparing with existing HMM recognizers. Based on this result, only optimal (recognition) codes were extracted in the actual DSP (TMS320C6711) environment, and the embedded speech recognition system was implemented. Similarly, the implementation result of the embedded system showed more improved recognition system implementation than existing solid HMM recognition systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• Journal of the Korea Computer Industry Society
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• v.3 no.3
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• pp.321-330
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• 2002

A 2-D median filter has many applications in various image and video signal processing areas. The rapid development in VLSI technology makes it possible to implement a real-time or near real-time 2-D median filter with reasonable cost. For the efficient VLSI implementation, the algorithm should have characteristics such as small memory requirements, regular computations, and local data transfers. This paper presents an architecture of the real-time two-dimensional separable median filter which has appropriate characteristics for the VLSI implementation. For the efficient two-dimensional median filter, a separable two-dimensional median filtering structure and a bit-sliced pipelined median searching algorithm are used. A behavioral simulator is implemented with C language and used for the analysis of the presented architecture.

• Smart Structures and Systems
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• v.15 no.1
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• pp.151-167
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• 2015

Instrumentation on structural health monitoring system imposes critical issues for applying the structural monitoring system to real world structures, for which not only on the configuration and geometry, but also aesthetics on the system to be monitored should be considered. To illustrate this point, two real world structural health monitoring systems, the structural health monitoring system of Shenzhen Vanke Center and the structural health monitoring system of Shenzhen Bay Stadium in China, are presented in the paper. The instrumentation on structural health monitoring systems of real world structures is addressed by providing the description of the structure, the purpose of the structural health monitoring system implementation, as well as details of the system integration including the installations on the sensors and acquisition equipment and so on. In addition, an intelligent algorithm on stress identification using measurements from multi-region is presented in the paper. The stress identification method is deployed using the fuzzy pattern recognition and Dempster-Shafer evidence theory, where the measurements of limited strain sensors arranged on structure are the input data of the method. As results, at the critical parts of the structure, the stress distribution evaluated from the measurements has shown close correlation to the numerical simulation results on the steel roof of the Beijing National Aquatics Center in China. The research work in this paper can provide a reference for the design and implementation of both real world structural health monitoring systems and intelligent algorithm to identify stress distribution effectively.

• The Journal of the Acoustical Society of Korea
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• v.38 no.1
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• pp.9-22
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• 2019

In this paper, we propose a method that can be applied to the efficient implementation of multi-channel active noise controller. Since the normalized MFxLMS (Modified Filtered-x Least Mean Square) algorithm for the multi-channel active noise control requires a large amount of computation, the difficulty has lied in implementing the algorithm using a low-cost MCU (Microcontoller Unit). We implement the multi-channel active noise controller efficiently by optimizing the software based on the features of the MCU. By maximizing the usage of single-cycle MAC (Multiply- Accumulate) operations and minimizing move operations of the delay memory, we can achieve more than 3 times the performance in the aspect of computational optimization, and by parellel processing using the auxillary processor included in the MCU, we can also obtain more than 4 times the performance. In addition, the usage of additional parts can be minimized by maximizing the usage of the peripherals embedded in the MCU.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.1
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• pp.69-85
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• 2003

In this paper, we discuss a validation test for cryptographic algorithms. The cryptographic algorithms decide on the security and the confidence of a security system protecting sensitive information. So. the implementation of cryptographic algorithms is very critical of the system. The validation lest specifies the procedures involved in validating implementations of the cryptographic standards and provides conformance testing for components or procedures of the algorithm. We propose a SEED Validation System(SVS) to verify that the implementation correctly performs the SEED algorithm. The SVS is composed of two types of validation tests, the Known Answer test and the Monte Carlo test. The System generates the testing data for the Known Answer tests and the random data for the Monte Carlo tests. This system can be used to validate and certify the cryptographic product.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.9-21
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• 2008

In this paper, we revisit a generally accepted opinion: implementing Elliptic Curve Cryptosystem (ECC) over GF$(2^m)$ on sensor motes using small word size is not appropriate because partial XOR multiplication over GF$(2^m)$ is not efficiently supported by current low-powered microprocessors. Although there are some implementations over GF$(2^m)$ on sensor motes, their performances are not satisfactory enough due to the redundant memory accesses that result in inefficient field multiplication and reduction. Therefore, we propose some techniques for reducing unnecessary memory access instructions. With the proposed strategies, the running time of field multiplication and reduction over GF$(2^{163})$ can be decreased by 21.1% and 24.7%, respectively. These savings noticeably decrease execution times spent in Elliptic Curve Digital Signature Algorithm (ECDSA) operations (Signing and verification) by around $15{\sim}19%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1142-1147
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• 2022

The edges of image should be detected first so that the objects in the image can be identified. An hardware-implemented edge detection algorithm outperforms its software version. Sobel operation is the most suitable algorithm for an hardware implementation of edge detection. And lots of works have been done to perform Sobel operations efficiently on FPGA-based hardware. This work proposes how to implement fast edge detection circuit on FPGA, which is based on the conventional circuit for edge detection using Sobel operator. The newly proposed circuit is suitable for processing images when the images are stored in memory devices and outperforms the conventional one with little additional FPGA resources. Both the conventional circuit and the proposed circuit were implemented on an FPGA. And the result showed that the proposed circuit almost doubles the performance in processing images and needs little additional FPGA resources.