• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.4
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• pp.585-592
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• 2014

In this paper, we study the LEA[1] block cipher system in UICC-16bit only. Also, we explain a key-schedule function and encryption/decryption structures, propose an advanced modified key-scheduling, and perform LEA in UICC-16bit that we proposed advanced modified key-scheduling. Also, we compare LEA with ARIA that proposed domestic standard block cipher, and we evaluate the efficiency on the LEA algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.770-772
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• 2013

Edges on the images are widely used in preprocessing in various areas including recognition and detection of the object. As generally known edge detection methods, there is a method using mask and these methods are Sobel, Prewitt, Roberts, Laplacian operator and etc. Implementation of these existing edge detection methods is simple. However, when processing the impulse noise added images, the properties of edge detection is not sufficient. Accordingly, in order to compensate for the weakness of existing edge detection methods and to detect strong edges on the images which were damaged by impulse noise, the edge detection algorithm using transformed mask was proposed in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.187-189
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• 2018

In this paper, the optimal design conditions for hardware implementation of the Secure Hash Algorithm3-512 (SHA3-512) hash function were analyzed. Five SHA3-512 hash cores with data-path of 64-bit, 320-bit, 640-bit, 960-bit, and 1600-bit were designed, and their functionality were verified by RTL simulation. Based on the results synthesized with Xilinx Virtex-5 FPGA device, we evaluated the performance of the SHA3-512 hash cores, including maximum frequency, throughput, and occupied slices. The analysis results show that the best hardware performance of SHA3-512 hash core can be achieved by designing it with 1600-bit data-path.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.102-109
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• 2003

In this paper, the new multiplicative algorithm using standard basis over GF(2m) is proposed. The multiplicative process is simplified by data select method in proposed algorithm. After multiplicative operation, the terms of degree greater than m can be expressed as a polynomial of standard basis with degree less than m by irreducible polynomial. For circuit implementation of proposed algorithm, we design the circuit using multiplexer and show the example over GF(24). The proposed architectures are regular and simple extension for m. Also, the comparison result show that the proposed architecture is more simple than privious multipliers. Therefore, it well suited for VLSI realization and application other operation circuits.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.4
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• pp.247-254
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• 2004

The mechanical informations such as the rotor speed and angle are required to operate the Cylindrical Permanent Magnet Synchronous Motor(PMSM). A resolver or encoder is typically used to supply the mechanical informations. This position sensor adds length to the machine, raises system cost, increases rotor inertia and requires additional devices. As the result, there has been a significant interest in the development of sensorless strategies to eliminate the position sensor. This paper presents an implementation of the new sensorless speed comtrol scheme for a PMSM. In the proposed algorithm, the line currents are estimated by a observer and the estimated speed can be yielded from the voltage equation because the information of speed is included in back emf. But the speed estimation error between the estimated and the real speeds is occured by errors due to measuring the motor parameters and sensing the line current and the input voltage. To minimize the speed estimations error, the estimated speeds are compensated by using an instantaneous reactive power in synchronously rotating reference frame. In this paper, the proposed algorithm is not affected by mechanical motor parameters because the mechanical equation is not used. The effectiveness of algorithm is confirmed by the experiments.

• ETRI Journal
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• v.27 no.4
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• pp.355-366
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• 2005

Automatic discovery of physical topology plays a crucial role in enhancing the manageability of modern metro Ethernet networks. Despite the importance of the problem, earlier research and commercial network management tools have typically concentrated on either discovering logical topology, or proprietary solutions targeting specific product families. Recent works have demonstrated that network topology can be determined using the standard simple network management protocol (SNMP) management information base (MIB), but these algorithms depend on address forwarding table (AFT) entries and can find only spanning tree paths in an Ethernet mesh network. A previous work by Breibart et al. requires that AFT entries be complete; however, that can be a risky assumption in a realistic Ethernet mesh network. In this paper, we have proposed a new physical topology discovery algorithm which works without complete knowledge of AFT entries. Our algorithm can discover a complete physical topology including inactive interfaces eliminated by the spanning tree protocol in metro Ethernet networks. The effectiveness of the algorithm is demonstrated by implementation.

• ETRI Journal
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• v.28 no.3
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• pp.320-328
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• 2006

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32-bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real-time. Also, we propose a hardware design for the algorithm on a field-programmable gate array (FPGA)-based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA-based solution can achieve a speed-up of 50 times over a software-based solution.

• Journal of the Korea Society of Computer and Information
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• v.22 no.5
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• pp.21-28
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• 2017

As technology related to digital imaging equipment is developed and generalized, digital imaging system is used for various purposes in fields of society. The object tracking technology from digital image data in real time is one of the core technologies required in various fields such as security system and robot system. Among the existing object tracking technologies, cam shift technology is a technique of tracking an object using color information of an object. Recently, digital image data using infrared camera functions are widely used due to various demands of digital image equipment. However, the existing cam shift method can not track objects in image data without color information. Our proposed tracking algorithm tracks the object by analyzing the color if valid color information exists in the digital image data, otherwise it generates the lightness feature information and tracks the object through it. The brightness feature information is generated from the ratio information of the width and the height of the area divided by the brightness. Experimental results shows that our tracking algorithm can track objects in real time not only in general image data including color information but also in image data captured by an infrared camera.

• ETRI Journal
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• v.37 no.4
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• pp.752-765
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• 2015

We propose a novel post-processing algorithm and its very-large-scale integration architecture that simultaneously uses the passive and active stereo vision information to improve the reliability of the three-dimensional disparity in a hybrid stereo vision system. The proposed architecture consists of four steps - left-right consistency checking, semi-2D hole filling, a tiny adaptive variance checking, and a 2D weighted median filter. The experimental results show that the error rate of the proposed algorithm (5.77%) is less than that of a raw disparity (10.12%) for a real-world camera image having a $1,280{\times}720$ resolution and maximum disparity of 256. Moreover, for the famous Middlebury stereo image sets, the proposed algorithm's error rate (8.30%) is also less than that of the raw disparity (13.7%). The proposed architecture is implemented on a single commercial field-programmable gate array using only 13.01% of slice resources, which achieves a rate of 60 fps for $1,280{\times}720$ stereo images with a disparity range of 256.

• ETRI Journal
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• v.33 no.5
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.