• Title/Summary/Keyword: implementation algorithm

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Design and Implementation of Upstream Channel Allocation Algorithm for DOCSIS 3.0 MAC (채널-결합 방식을 사용하는 상향대역 할당 알고리즘 성능 검증을 위한 DOCSIS 3.0 시뮬레이터 설계 및 구현)

  • Kim, Tae-Kyoon;Ra, Sung-Woong
    • Journal of the Korea Society for Simulation
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    • v.17 no.4
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    • pp.21-27
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    • 2008
  • In this paper, we design and implement the upstream packet bandwidth allocation algorithm on OPNET-based DOCSIS 3.0 simulator including channel-bonding CM (Cable Modem)s. Previous DOCSIS CM could not support channel bonding, it has problem in upstream bandwidth allocation and determine the contention area. The proposed upstream bandwidth allocation algorithm has been improved the queuing time and success rate. For the simulation, we design the MAC frame structure with channel bonding supported CM and not. And then, this paper design and implement the CMTS node model, CM node model, CMTS process model, and CM process model.

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An Implementation of Selection Algorithm for Efficient Scheduling on Real-Time Linux Environment (실시간 Linux 환경에서 효율적인 스케쥴링을 위한 선택 알고리즘의 구현)

  • 김성락
    • Journal of the Korea Society of Computer and Information
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    • v.7 no.2
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    • pp.1-8
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    • 2002
  • By now, Schedulers for RMS and EDF are implemented for real-time Linux Scheduler. These Schedulers are used for do not consider there's characteristics. Missing Schedulability-test cause result that increase deadline miss rate. Also The present real-time Linux causes system halt Because of scheduling for unschedulable tasks . These appearances are very fatal for real-time system. Therefor, In this paper The peaceful schedulability-test use scheduler which is proper characteristics of RMS and EDF scheduling methods. This scheduler keeps deadline and eliminates system halt from scheduling unschedulable tasks. In this paper, we propose the schedulability-test algorithm and scheduler select algorithm for the effective management of tasks sets.

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An Implementation of a Thinning Algorithm using FPGA (세선화 알고리즘의 FPGA 구현)

  • Jung, Seung-Min;Yeo, Hyeop-Goo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.719-721
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    • 2013
  • A thinning stage of fingerprint algorithm occupies 39% cycle of microprocessor system for identification processing of image from fingerprint sensor. Hardware block processing is more effective than software one in speed and power consumption, because a thinning algorithm is iteration of simple instructions without a transcendental function. This paper describes an effective hardware scheme for thinning stage processing using Verilog-HDL in $64{\times}64$ Pixel Array. The hardware scheme is designed and simulated in RTL. The logic is also synthesized by XST in FPGA environment and tested. Experimental results show the performance of the proposed scheme and possibility of application for a soft microprocessor and thinning processor embedded fingerprint SoC.

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Real-time small target detection method Using multiple filters and IPP Libraries in Infrared Images

  • Kim, Chul Joong;Kim, Jae Hyup;Jang, Kyung Hyun
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.8
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    • pp.21-28
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    • 2016
  • In this paper, we propose a fast small target detection method using multiple filters, and describe system implementation using IPP libraries. To detect small targets in Infra-Red images, it is mandatory that you should apply a filter to eliminate a background and identify the target information. Moreover, by using a suitable algorithm for the environments and characteristics of the target, the filter must remove the background information while maintaining the target information as possible. For this reason, in the proposed method we have detected small targets by applying multi area(spatial) filters in a low luminous environment. In order to apply the multi spatial filters, the computation time can be increased exponentially in case of the sequential operation. To build this algorithm in real-time systems, we have applied IPP library to secure a software optimization and reduce the computation time. As a result of applying real environments, we have confirmed a detection rate more than 90%, also the computation time of the proposed algorithm have been improved about 90% than a typical sequential computation time.

A Study on Extracting Valid Speech Sounds by the Discrete Wavelet Transform (이산 웨이브렛 변환을 이용한 유효 음성 추출에 관한 연구)

  • Kim, Jin-Ok;Hwang, Dae-Jun;Baek, Han-Uk;Jeong, Jin-Hyeon
    • The KIPS Transactions:PartB
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    • v.9B no.2
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    • pp.231-236
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    • 2002
  • The classification of the speech-sound block comes from the multi-resolution analysis property of the discrete wavelet transform, which is used to reduce the computational time for the pre-processing of speech recognition. The merging algorithm is proposed to extract vapid speech-sounds in terms of position and frequency range. It performs unvoiced/voiced classification and denoising. Since the merging algorithm can decide the processing parameters relating to voices only and is independent of system noises, it is useful for extracting valid speech-sounds. The merging algorithm has an adaptive feature for arbitrary system noises and an excellent denoising signal-to-noise ratio and a useful system tuning for the system implementation.

Implementation of Spectrum Sensing Module using STFT Method (STFT 기법을 적용한 스펙트럼 센싱 모듈 구현)

  • Lee, Hyun-So;Kang, Min-Kyu;Moon, Ki-Tak;Kim, Kyung-Seok
    • The Journal of the Korea Contents Association
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    • v.10 no.1
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    • pp.78-86
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    • 2010
  • The Spectrum Sensing Technology is the core technology of the Cognitive Radio (CR) System that is one of the future wireless communication technologies. In this paper, we proposed the efficient Spectrum Sensing Method using the Short Time Fourier Transform (STFT) that is the algorithm for Time-Frequency analysis of the raw data. Applied window function to STFT algorithm is a Kaiser window, it is piled up its 50% range. For the simulation, the DVB-H signal with the 6MHz bandwidth is used as the Input Signal. And we confirm the Spectrum Sensing result using Modified Periodogram Method, Welch's Method for compared with Short Time Fourier Transform Algorithm. And also, Spectrum Sensing Module is implemented using embedded board.

Algorithm and Hardware Implementation of Redeye Correction Using the Redeye Features (적목현상 특징을 이용한 적목현상 보정 알고리즘 및 하드웨어 구현)

  • Lee, Song-Jin;Jang, Won-Woo;Choi, Won-Tae;Kim, Suk-Chan;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.3
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    • pp.151-157
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    • 2009
  • In this paper, we proposed an algorithm of redeye correction. For naturally redeye correction, we assumed positions of the redeye at an image which produced redeye, and we estimated rate of the redeye to apply the appropriate redeye correction suitably. We extract and label pixels those are possible of generating redeye using red, skin and reflected light color. The each labeled group is decided by rates of length and width, dimension, density, the color of white of the eye and reflected light color of groups for the redeye group. We corrected positions of redeye using blurring effect, naturally. In the case of designing the proposed algorithm, we designed the redeye correction hardware using the minimum of memories for efficiency of hardware.

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Illumination-Robust Lane Detection Algorithm using CIEL *C*h (CIEL * C * h를 이용한 조도변화에 강인한 차선 인식 연구)

  • Pineda, Jose Angel;Cho, Yoon-Ji;Sohn, Kwang-hoon
    • Annual Conference of KIPS
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    • 2017.11a
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    • pp.891-894
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    • 2017
  • Lane detection algorithms became a key factor of advance driver assistance system (ADAS), since the rapidly increasing of high-technology in vehicles. However, one common problem of these algorithms is their performance's instability under various illumination conditions. We recognize a feasible complementation between image processing and color science to address the problem of lane marks detection on the road with different lighting conditions. We proposed a novel lane detection algorithm using the attributes of a uniform color space such as $CIEL^*C^*h$ with the implementation of image processing techniques, that lead to positive results. We applied at the final stage Clustering to make more accurate our lane mark estimation. The experimental results show the effectiveness of our method with detection rate of 91.80%. Moreover, the algorithm performs satisfactory with changes in illumination due to our process with lightness ($L^*$) and the color's property on $CIEL^*C^*h$.

Implementation of a Feature Extraction Chip for High Speed OCR (고속 문자 인식을 위한 특정 추출용 칩의 구현)

  • 김형구;강선미;김덕진
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.6
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    • pp.104-110
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    • 1994
  • We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.

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Design of Neural Network based MPPT(Maximum Power Point Tracking) Algorithm for Efficient Energy Management in Urban Wind Turbine Generating System (도시형 풍력발전 시스템의 효율적 에너지 관리를 위한 인공신경망 기반 최대 전력점 추종 알고리즘 개발)

  • Kim, Seung-Young;Kim, Sung-Ho
    • Journal of the Korean Institute of Intelligent Systems
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    • v.19 no.6
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    • pp.766-772
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    • 2009
  • Generally, wind industry has been oriented to large power systems which require large windy areas and often need to overcome environment restrictions. However, small-scale wind turbines are closer to the consumers and have a large market potential, and much more efforts are required to become economically attractive. In this paper, a prototype of a small-scale urban wind generation system for battery charging application is described and a neural network based MPPT(Maximum Power Point Tracking) algorithm which can be effectively applied to urban wind turbine system is proposed. Through Matlab based simulation studies and actual implementation of the proposed algorithm, the feasibility of the proposed scheme is verified.