• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.335-341
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• 1998

In this paper, we present a real time implementation of CS-ACELP(Conjugate Structure Algebraic Code Excited Linear Prediction) speech coder. ITU-T has standardized the CS-ACELP algorithm as G.729. Areal-time implementation of CS-ACELP speech coder algorithm is achieved using 16 bit fixed-point DSP chip. To implement in fixed-point DSP Chip, integer simulation of CS-ACELP algorithm is used. Furthermore. input/output function and communication function included in CS-ACELP speech coder is described. We develope CS-ACELP speech coder in DSP evaluation board and evaluate in IMT-2000 Test-bed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.4
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• pp.388-393
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• 2019

As a fiiting method to data with outliers, RANSAC(RANdom SAmple Consensus) based algorithm is widely used in fitting of line, circle, ellipse, etc. CUDA is currently most widely used GPU with massive parallel processing capability. This paper proposes an efficient CUDA implementation of multiple planes fitting using RANSAC with 3d points data, of which one set of 3d points is used for one plane fitting. The performance of the proposed algorithm is demonstrated compared with CPU implementation using both artificially generated data and real 3d heights data of a PCB. The speed-up of the algorithm over CPU seems to be higher in data with lower inlier ratio, more planes to fit, and more points per plane fitting. This method can be easily applied to a wide variety of other fitting applications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.66-77
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• 2002

This paper deals with an implementation of the navigation parameter extraction technique using the TMS320C80 multimedia video processor (MVP). Especially, this Paper focuses on the relative position estimation algorithm which plays an important role in real-time operation of the overall system. Based on the relative position estimation algorithm using the images obtained at two locations, we develop a fast algorithm that can reduce large amount of computation time and fit into fixed-point processors. Then, the algorithm is reconfigured for parallel processing using the 4 parallel processors in the MVP. As a result, we shall demonstrate that the navigation parameter extraction system employing the MVP can operate at full-frame rate, satisfying real-time requirement of the overall system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.104-110
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• 2008

In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.97-107
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• 2004

This paper presents an System-on-Chip(SoC) implementation of fingerprint feature extraction system. Typical fingerprint feature extraction systems employ binarization and thinning processes which cause many extraction errors for low qualify fingerprint images and degrade the accuracy of the entire fingerprint recognition system. To solve these problems, an algorithm directly following ridgelines without the binarization and thinning process has been proposed. However, the computational requirement of the algorithm makes it hard to implement it on SoCs by using software only. This paper presents an implementation of the ridge-following algorithm onto SoCs. The algorithm has been modified to increase the efficiency of hardwares. Each function block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The fingerprint feature extraction system has been developed as an IP for SoCs, hence it can be used on many kinds of SoCs for smart cards.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.50-58
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• 2006

This paper describes the implementation of an efficient Rate-Distortion Optimization algerian to speed up rate control in JPEG2000. While the conventional algorithm determines the rate constant by averaging maximum R-D slope and minimum R-D slope for entire image, the proposed algorithm determines it by using R-D slopes of coding passes located near truncation point. Moreover, the rate allocation in proposed algorithm is conducted about only coding passes excluded from the previous rate allocation. As a result, it can reduce the number of operations required for rate-distortion optimization. The proposed algorithm was implemented in C programing language and was executed on the Altera Excalibur(EPXA4) development board.

• Journal of IKEEE
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• v.22 no.1
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1389-1399
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• 2015

This research suggests maximum power point tracking (MPPT) for the solar photovoltaic (PV) power scheme using a new constant voltage (CV) fractional order incremental conductance (FOINC) algorithm. The PV panel has low transformation efficiency and power output of PV panel depends on the change in weather conditions. Possible extracting power can be raised to a battery load utilizing a MPPT algorithm. Among all the MPPT strategies, the incremental conductance (INC) algorithm is mostly employed due to easy implementation, less fluctuations and faster tracking, which is not only has the merits of INC, fractional order can deliver a dynamic mathematical modelling to define non-linear physiognomies. CV-FOINC variation as dynamic variable is exploited to regulate the PV power toward the peak operating point. For a lesser scale photovoltaic conversion scheme, the suggested technique is validated by simulation with dissimilar operating conditions. Contributions are made in numerous aspects of the entire system, including new control algorithm design, system simulation, converter design, programming into simulation environment and experimental setup. The results confirm that the small tracking period and practicality in tracking of photovoltaic array.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.740-756
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• 2017

This paper proposes a feedback-linearization-based control algorithm for multirotor unmanned aerial vehicles (UAVs). The feedback linearization scheme is highly efficient for considering nonlinearity between the rotational and translational motion of multirotor UAVs. We also propose a dynamic equation that reflects the aerodynamic effects of the vehicles; the equation's parameters can be determined through curve fitting using actual flight data. We derive the feedback linearization controller from the proposed dynamic equation, and propose a Luenberger observer to attenuate measurement noises. The proposed algorithm is implemented using our in-house flight control computer, and we describe its implementation in detail. To investigate the performance of the proposed algorithm, we carry out two flight scenarios: the first scenario, an autonomous landing on a moving platform, is a test of maneuverability; the second, picking up and replacing an object, test the algorithm's accuracy. In these scenarios, the proposed algorithm precisely controls multirotor UAVs, and we confirm that it can be successfully applied to real flight environments.