• Title/Summary/Keyword: implementation algorithm

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A Time-Varying Gain Super-Twisting Algorithm to Drive a SPIM

  • Zaidi, Noureddaher;Jemli, Mohamed;Azza, Hechmi Ben;Boussak, Mohamed
    • Journal of Power Electronics
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    • v.13 no.6
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    • pp.955-963
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    • 2013
  • To acquire a performed and practical solution that is free from chattering, this study proposes the use of an adaptive super-twisting algorithm to drive a single-phase induction motor. Partial feedback linearization is applied before using a super-twisting algorithm to control the speed and stator currents. The load torque is considered an unknown but bounded disturbance. Therefore, a time-varying switching gain that does not require prior knowledge of the disturbance boundary is proposed. A simple sliding surface is formulated as the difference between the real and desired trajectories obtained from the indirect rotor flux oriented control strategy. To illustrate the effectiveness of the proposed control structure, an experimental setup around a digital signal processor (dS1104) is developed and several tests are performed.

Optimal Estimation of Rock Mass Properties Using Genetic Algorithm (유전알고리즘을 이용한 암반 물성의 최적 평가에 관한 연구)

  • Hong Changwoo;Jeon Seokwon
    • Tunnel and Underground Space
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    • v.15 no.2 s.55
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    • pp.129-136
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    • 2005
  • This paper describes the implementation of rock mass rating evaluation based on genetic algorithm(GA) and conditional simulation technique to estimate RMR in the area without sufficient borehole data RMR were estimated by GA and conditional simulation technique with reflecting distribution feature and spatial correlation. And RMR determined by GA were compared with the results from kriging. Through the analysis of the results from 30 simulations, the uncertainty of estimation could be quantified.

Neural PID Based MPPT Algorithm for Photovoltaic Generator System (태양광 발전시스템을 위한 신경회로망 PID 기반 MPPT 알고리즘)

  • Park, Ji-Ho;Cho, Hyun-Cheol;Kim, Dong-Wan
    • New & Renewable Energy
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    • v.8 no.3
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    • pp.14-22
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    • 2012
  • Performance of photovoltaic (PV) generator systems relies on its operating conditions. Maximum power extracted from PV generators depends strongly on solar irradiation, load impedance, and ambient temperature. A most maximum power point tracking (MPPT) algorithm is based on a perturb and observe method and an incremental conductance method. It is well known the latter is better in terms of dynamics and tracking characteristics under condition of rapidly changing solar irradiation. However, in case of digital implementation, the latter has some error for determining a maximum power point. This paper presents a PID based MPPT algorithm for such PV systems. We use neural network technique for determining PID parameters by online learning approach. And we construct a boost converter to regulate the output voltage from PV generator system. Computer simulation is carried out to evaluate the proposed MPPT method and we accomplish comparative study with a perturb and observe based MPPT method to prove its superiority.

Operation Algorithm of Battery Energy Storage System (BESS) for Saving Electric Charges (전기요금 절감 측면에서 에너지저장시스템의 운전알고리즘)

  • 김응상
    • Journal of Energy Engineering
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    • v.8 no.4
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    • pp.519-524
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    • 1999
  • this paper proposes the operation algorithm of 1MW class Battery Energy Storage System(BESS) installed at the extra-high voltage customer. The objective of the proposed algorithm is to reduce electric charges during the operation of the BESS interconnected to power system. This paper simulates the electric charges in 1998 considering Season and Time of Use Rate and Power Factor in the assumption that electricity demand in 1998 is the same amount of that in 1997 and shows the saving of about 40 million won in the total electric charges. The results comparing the real electric charges of June. July and August in 1997 with that in 1998 show that the implementation of the proposed algorithm could significantly reduce electric charges during the operation the BESS.

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Design of MUSIC Algorithm for DOA estimation (도래방향 추정을 위한 MUSIC 알고리즘의 설계)

  • Park, Byung-Woo;Jeong, Bong-Sik
    • Journal of the Institute of Convergence Signal Processing
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    • v.7 no.4
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    • pp.189-194
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    • 2006
  • In this paper, design of MUSIC algorithm, which is one of high resolution DOA (direction of arrival) estimation techniques was studied. Generally the complex-valued correlation matrix of MUSIC algorithm is transformed to unitary matrix or matrix expansion for the real hardware implementation. Using the orthogonality between the noise subspace eigenvectors and the steering vectors corresponding to signal component, we estimate DOA with the real-valued computation between steering vectors and noise subspace eigenvectors. The DOA algorithm was designed with VHDL models with considerations of 2 elements and 1 incident wave and its simulation results are derived.

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Implementation of Advanced Frequency Measurement Algorithm (DSP를 이용한 개선된 주파수 측정 알고리즘 구현)

  • Lee, Jung-woo;An, Jong-hyun;Oh, Yong-taek
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.465-468
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    • 2009
  • A frequency in electrical power system changes by the load fluctuation in utility grid, has an influence on a connected generator, and ultimately brings a big trouble in the power system. Therefore, a quick measurement of system frequency and governor control of power system is a very important factor in the reliability and the economic feasibility. In this study, An improve algorithm that measures the power system frequency quickly and accurately is suggested, simulated by using Matlab and programmed using C code through DSP6713 KIT. This algorithm is tested to the arbitrary voltage waveform input. The results show that the suggested algorithm is effective in the accurate and quick frequency measurements.

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Implementation and Application of Multiple Local Alignment (다중 지역 정렬 알고리즘 구현 및 응용)

  • Lee, Gye Sung
    • The Journal of the Convergence on Culture Technology
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    • v.5 no.3
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    • pp.339-344
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    • 2019
  • Global sequence alignment in search of similarity or homology favors larger size of the sequence because it keeps looking for more similar section between two sequences in the hope that it adds up scores for matched part in the rest of the sequence. If a substantial size of mismatched section exists in the middle of the sequence, it greatly reduces the total alignment score. In this case a whole sequence would be better to be divided into multiple sections. Overall alignment score over the multiple sections of the sequence would increase as compared to global alignment. This method is called multiple local alignment. In this paper, we implement a multiple local alignment algorithm, an extension of Smith-Waterman algorithm and show the experimental results for the algorithm that is able to search for sub-optimal sequence.

The FPGA Implementation of The Viterbi Algorithm for Error Correcting (에러 정정을 위한 Viterbi 알고리즘의 FPGA 구현)

  • 조현숙;한승조;이상호
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.9 no.1
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    • pp.115-126
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    • 1999
  • As the processing speed of communication and computer system has been improved, high speed data processing is required to correct error of data. In this paper, decoding algorithm which is applicable to the wireless communication system is proposed and encoder and decoder are designed by using the proposed decoding algorithm. We design the encoder and decoder by using the VHDL(VHSIC Hardware Description Language) and simulate the designed encoder and decoder by using V-system. Designed algorithm is synthesized by using synopsys tools and is made to one chip by means of XILINX XC4010EPC84-4. When 20MHz was used as the input clock, data arrival time was 29.20ns and data require time was 48.70ns.

An Efficient Hardware Implementation of AES Rijndael Block Cipher Algorithm (AES Rijndael 블록 암호 알고리듬의 효율적인 하드웨어 구현)

  • 안하기;신경욱
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.2
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    • pp.53-64
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    • 2002
  • This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

Dynamic Prime Chunking Algorithm for Data Deduplication in Cloud Storage

  • Ellappan, Manogar;Abirami, S
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.4
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    • pp.1342-1359
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    • 2021
  • The data deduplication technique identifies the duplicates and minimizes the redundant storage data in the backup server. The chunk level deduplication plays a significant role in detecting the appropriate chunk boundaries, which solves the challenges such as minimum throughput and maximum chunk size variance in the data stream. To provide the solution, we propose a new chunking algorithm called Dynamic Prime Chunking (DPC). The main goal of DPC is to dynamically change the window size within the prime value based on the minimum and maximum chunk size. According to the result, DPC provides high throughput and avoid significant chunk variance in the deduplication system. The implementation and experimental evaluation have been performed on the multimedia and operating system datasets. DPC has been compared with existing algorithms such as Rabin, TTTD, MAXP, and AE. Chunk Count, Chunking time, throughput, processing time, Bytes Saved per Second (BSPS) and Deduplication Elimination Ratio (DER) are the performance metrics analyzed in our work. Based on the analysis of the results, it is found that throughput and BSPS have improved. Firstly, DPC quantitatively improves throughput performance by more than 21% than AE. Secondly, BSPS increases a maximum of 11% than the existing AE algorithm. Due to the above reason, our algorithm minimizes the total processing time and achieves higher deduplication efficiency compared with the existing Content Defined Chunking (CDC) algorithms.