• Journal of Institute of Control, Robotics and Systems
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• v.13 no.5
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• pp.399-405
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• 2007

This paper deals with the controller for a stable walking of a humanoid robot using genetic algorithm. A humanoid robot has instability during walking because it isn't fixed on the ground, and its nonlinearities of the joints increase its instability. If controller isn't robust, the robot may fall down at the ground during walking because of its nonlinearities. To solve this problem, robust controller is required to reduce the effect of nonlinearities and to gain the good tracking performance. In this paper, motion controller that is based on fuzzy-sliding mode controller is proposed. This controller can remove the effect of the saturation by limitation of the input voltage. It also includes compensator for reducing the effect of the nonlinearity by backlash and PI controller improving the tracking performance. In here, genetic algorithm is used for searching the optimal gains of the controller. From the given controller, a humanoid robot can moved more preciously. All the processes are investigated through simulations and are verified experimentally in a real joint system for a humanoid robot.

• The Journal of the Acoustical Society of Korea
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• v.14 no.1
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• pp.13-21
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• 1995

In this paper, we improve an image classifier algorithm based on neural network learning. It consists of two steps. The first is input pattern generation and the second, the global neural network implementation using an improved back-propagation algorithm. The feature vector for pattern recognition consists of the codebook data obtained from self-organization feature map learning. It decreases the input neuron number as well as the computational cost. The global neural network algorithm which is used in classifier inserts a control part and an address memory part to the back-propagation algorithm to control weights and unit-offsets. The simulation results show that it does not fall into the local minima and can implement easily the large-scale neural network. And it decreases largely the learning time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.12-19
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• 2007

This paper proposes the enhanced auto-focus algorithm detecting several objects and selecting the target object. Proposed algorithm first detects some objects distributed in the image using focus measure operator and multi-window and then selects the target object through fuzzy reasoning with three fuzzy membership functions. Implementation can be simple because it only needs image sensor instead of infrared or ultrasonic equipment. Experimental result shows that the proposed algorithm can improve the quality of image by focusing to the target object.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.401-403
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• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.371-373
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• 2015

This paper describes an analysis of hardware design conditions of moving object detection algorithm which is based on effective Gaussian mixture learning (EGML). The simulation model of EGML algorithm is implemented using OpenCV, and it is analyzed that the effects of parameter values on background learning time and moving object detection sensitivity for various images. In addition, optimal design conditions for hardware implementation of EGML-based MOD algorithm are extracted from fixed-point simulations for various bit-width parameters.

• Journal of Power Electronics
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• v.10 no.3
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• pp.313-319
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• 2010

This paper proposes a new compensation algorithm for the current measurement errors in a DFIG (Doubly Fed Induction Generator). Generally, current measurement path with current sensors and analog devices has non-ideal factors like offset and scaling errors. As a result, the dq-axis currents of the synchronous reference frame have one and two times ripple components of the slip frequency. In this paper, the main concept of the proposed algorithm is implemented by integrating the 3-phase rotor currents into the stationary reference frame to compensate for the measured current ripples in a DFIG. The proposed algorithm has several beneficial features: easy implementation, less computation time, and robustness with regard to variations in the electrical parameters. The effectiveness of the proposed algorithm is verified by several experiments.

• Journal of Power Electronics
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• v.17 no.1
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• pp.253-261
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• 2017

For a single-phase active power filter (APF), designing a more efficient algorithm to guarantee accurate and fast harmonics extraction with a lower computing cost is still a meaningful topic. The common idea still employs a IRPT-based Park transform, which was originally designed for 3-phase applications. Therefore, an additional virtual signal generation (VSG) link is necessary when it is used in the single-phase condition. This method, with virtual signal generation and transform, is obviously not the most efficient one. Regarding this problem, this paper proposes a novel harmonics extraction algorithm to further improve efficiency. The new algorithm is based on the principle of trigonometric orthogonal functions (TOF), and its mathematical principle and physical meaning are introduced in detail. Its implementation and superiority in terms of computation efficiency are analyzed by comparing it with conventional methods. Finally, its effectiveness is well validated through detailed simulations and laboratory experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.822-830
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• 2014

Recently, A Security service in Internet environments has been more important and the use of SSL & TLS is increasing for the personel homepage as well as administrative institutions. Also, IETF suggests using DTLS, which can provide a security service to constrained devices with lower CPU power and limited memory space under IoT environments. In this paper, we implement LEA(Lightweight Encryption Algorithm) algorithm and apply it to OpenSSL. The implemented algorithm is compared with other symmetric encryption algorithms such as AES etc, and it shows the superior performance in calculation speed.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.8
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• pp.360-367
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• 2002

In this paper, genetic algorithm based adaptive image enhancement filtering scheme is proposed and Implemented on FPGA board. Conventional filtering methods require a priori noise information for image enhancement. In general, if a priori information of noise is not available, heuristic intuition or time consuming recursive calculations are required for image enhancement. Contrary to the conventional filtering methods, the proposed filter system can find optimal combination of filters as well as their sequent order and parameter values adaptively to unknown noise types using structured genetic algorithms. The proposed image enhancement filter system is mainly composed of two blocks. The first block consists of genetic algorithm part and fitness evaluation part. And the second block consists of four types of filters. The first block (genetic algorithms and fitness evaluation blocks) is implemented on host computer using C code, and the second block is implemented on re-configurabe FPGA board. For gray scale control, smoothing and deblurring, four types of filters(median filter, histogram equalization filter, local enhancement filter, and 2D FIR filter) are implemented on FPGA. For evaluation, three types of noises are used and experimental results show that the Proposed scheme can generate optimal set of filters adaptively without a pioi noise information.