• Journal of IKEEE
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• v.27 no.4
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• pp.624-629
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• 2023

Estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that estimates the angle of a signal arriving at an array antenna using the shift invariance property of an array antenna. ESPRIT offers the good trade-off between performance and complexity. However, the ESPRIT algorithm still requires high-complexity operations such as covariance matrix and eigenvalue decomposition, so implementation with a hardware processor is essential to estimate the angle of arrival in real time. In addition, ESPRIT processors should have high performance. The performance is related to the number of antennas, and the number of antennas required for each application are different. Therefore, we proposed an ESPRIT processor that provides 2 to 8 variable antenna configurations to meet the performance and complexity requirements according to the applied field. The proposed ESPRIT processor was designed using the Verilog-HDL and implemented on a field programmable gate array (FPGA).

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.11-17
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• 2020

In this paper, we propose practical results for cache replacement policy by measuring cache hit and search time for each replacement algorithm through cache simulation. Thus, the structure of each cache memory and the four types of alternative policies of FIFO, LFU, LRU and Random were implemented in software to analyze the characteristics of each technique. The paper experiment showed that the LRU algorithm showed hit rate and search time of 36.044% and 577.936ns in uniform distribution, 45.636% and 504.692ns in deflection distribution, while the FIFO algorithm showed similar performance to the LRU algorithm at 36.078% and 554.772ns in even distribution and 45.662% and 489.574ns in bias distribution. Then LFU followed, Random algorithm was measured at 30.042% and 622.866ns at even distribution, 36.36% at deflection distribution and 553.878ns at lowest performance. The LRU replacement method commonly used in cache memory has the complexity of implementation, but it is the most efficient alternative to conventional alternative algorithms, indicating that it is a reasonable alternative method considering the reference information of data.

• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.503-518
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• 2012

In this paper, we propose a complexity-based parallelization method of the sample adaptive offset (SAO) algorithm which is one of HEVC in-loop filters. The SAO algorithm can be regarded as region-based process and the regions are obtained and represented with a quad-tree scheme. A offset to minimize a reconstruction error is sent for each partitioned region. The SAO of the HEVC can be parallelized in data-level. However, because the sizes and complexities of the SAO regions are not regular, workload imbalance occurs with multi-core platform. In this paper, we propose a LCU-based SAO algorithm and a complexity prediction algorithm for each LCU. With the proposed complexity-based LCU processing, we found that the proposed algorithm is faster than the sequential implementation by a factor of 2.38 times. In addition, the proposed algorithm is faster than regular parallel implementation SAO by 21%.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.29-39
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• 2015

This paper describes a design and implementation of fuzzy-based algorithm for hand-shake state detection and error compensation in the mobile optical image stabilization(OIS) motion detector. Since the gyro sensor output of the OIS motion detector includes inherent error signals, accurate error correction is required for prompt hand-shake error compensation and stable hand-shake state detection. In this research with a little computation overhead of fuzzy-based algorithm, the hand-shake error compensation could be improved by quickly reducing the angle and phase error for the hand-shake frequencies. Further, stability of the OIS system could be enhanced by the hand-shake states of {Halt, Little vibrate, Big vibrate, Pan/Tilt}, classified by subdividing the hand-shake angle. The performance and stability of the proposed algorithm in OIS motion detector is quantitatively and qualitatively evaluated with the emulated hand-shaking of ${\pm}0.5^{\circ}$, ${\pm}0.8^{\circ}$ vibration and 2~12Hz frequency. In experiments, the average error compensation gain of 3.71dB is achieved with respect to the conventional BACF/DCF algorithm; and the four hand-shake states are detected in a stable manner.

• Journal of Power Electronics
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• v.14 no.1
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• pp.61-73
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• 2014

Multiphase machines are characterized by high power density, enhanced fault-tolerant capacity, and low torque pulsation. For a voltage source inverter supplied multiphase machine, the probability of load imbalances becomes greater and unwanted low-order stator voltage harmonics occur. This paper deals with the PWM control of multiphase inverters under unbalanced load conditions and it proposes a novel near-five-vector SVPWM algorithm based on the five-phase six-leg inverter. The proposed algorithm can output symmetrical phase voltages under unbalanced load conditions, which is not possible for the conventional SVPWM algorithms based on the five-phase five-leg inverters. The cause of extra harmonics in the phase voltages is analyzed, and an xy coordinate system orthogonal to the ${\alpha}{\beta}z$ coordinate system is introduced to eliminate low-order harmonics in the output phase voltages. Moreover, the digital implementation of the near-five-vector SVPWM algorithm is discussed, and the optimal approach with reduced complexity and low execution time is elaborated. A comparison of the proposed algorithm and other existing PWM algorithms is provided, and the pros and cons of the proposed algorithm are concluded. Simulation and experimental results are also given. It is shown that the proposed algorithm works well under unbalanced load conditions. However, its maximum modulation index is reduced by 5.15% in the linear modulation region, and its algorithm complexity and memory requirement increase. The basic principle in this paper can be easily extended to other inverters with different phase numbers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1876-1882
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• 1999

In this paper, we have proposed a FCB detection algorithm for the GSM system which is european cellular standard. The detection algorithm can be implemented using received signal sampler, correlator, and post detection combiner. GSM mobile phone can use the proposed algorithm for detection of the Broadcasting Channel, and to obtain the initial timing estimate. The proposed algorithm has a architecture which is suitable for DSP or ASIC implementation, and required memory size is small. The performance of the algorithm is a function of the processing data window size and the threshold values. Proper window size and the threshold values can be determined by analyzing the correlator and combiner. The proposed algorithm has been implemented using DSP, and the performance was verified using baseband simulation. The simulation assumed frequency offset values of 0ppm and 15ppm with the receiver filter bandwidth set at both minimum and maximum. It is shown that the algorithm is robust under various assumptions, and suitable for real implementations.

• The Journal of Industrial Distribution & Business
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• v.10 no.11
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• pp.71-80
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• 2019

Purpose: The purpose of this study is to design the curriculum of Basic College Software Programming to develop creative and logical-thinking. This course is guided by algorithmic thinking and logical thinking that can be solved by computing for problem-solving, and it helps to develop by software through basic programming education. Through the stage of problem analysis, abstraction, algorithm, data structure, and algorithm implementation, the curriculum is designed to help learners experience algorithm problem-solving in various areas to develop diffusion thinking. For Learners aim to achieve the balanced development of divergent and convergent-thinking needed in their creative problem-solving skills. Research design, data and methodology: This study is to design a basic software education for improving algorithm-thinking for non-major. The curriculum designed in this paper is necessary to non-majors students who have completed the 'Creative Thinking and Coding Course' Design Thinking based are targeted. For this, contents were extracted through advanced research analysis at home and abroad, and experts in computer education, computer engineering, SW education, and education were surveyed in the form of quasi-openness. Results: In this study, based on ADD Thinking's algorithm thinking, we divided the unit college majors into five groups so that students of each major could accomplish the goal of "the ability to internalize their own ideas into computing," and extracted and designed different content areas, content elements and sub-components from each group. Through three expert surveys, we established a strategy for characterization by demand analysis and major/textbook category and verified the appropriateness of the design direction to ensure that the subjects and contents of the curriculum are appropriate for each family in order to improve algorithm-thinking. Conclusions: This study helps develop software by enhancing the ability of students who practice various subjects and exercises to explore creative expressions in various areas, such as 'how to think like a computer' that can implement and execute their ideas in computing. And it helps increase the ability to think logical and algorithmic computing based on creative solutions, improving problem-solving ability based on computing thinking and fundamental understanding of computer coding and development of logical thinking ability through programming.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.586-594
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• 2003

X-Match algorithm is a lossless compression algorithm suitable for hardware implementation owing to its simplicity. It can compress 32 bits per clock cycle and is suitable for real time compression. However, as the bus width increases 64-bit, the compression unit also need to increase. This paper proposes the cooperative parallel X-Match (X-MatchCP) algorithm, which improves the compression speed by performing the two X-Match algorithms in parallel. It searches the all dictionary for two words, combines the compression codes of two words generated by parallel X-Match compression and outputs the combined code while the previous parallel X-Match algorithm searches an individual dictionary. The compression ratio in X-MatchCP is almost the same as in X-Match. X-MatchCP algorithm is described and simulated by Verilog hardware description language.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.126-131
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• 2004

Full search algorithm(FA) provides the best performance but this is usually impractical because of the large number of computations required for large search region. Fast search and conventional Boolean matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than FA. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.95-105
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• 2002

This paper describes an efficient method to implement a hardware circuit of RSA public key cryptographic algorithm, which is important to public-key cryptographic system for an authentication, a key exchange and a digital signature. The RSA algorithm needs a modular exponential for its cryptographic operation, and the modular exponential operation is consists of repeated modular multiplication. In a numerous algorithm to compute a modular multiplication, the Montgomery algorithm is one of the most widely used algorithms for its conspicuous efficiency on hardware implementation. Over the past a few decades a considerable number of studies have been conducted on the efficient hardware design of modular multiplication for RSA cryptographic system. But many of those studies focused on the decrease of operating time for its higher performance. The most important thing to design a hardware circuit, which has a limit on a circuit area, is a trade off between a small circuit area and a feasible operating time. For these reasons, we modified the Montgomery algorithm for its efficient hardware structure for a system having a limit in its circuit area and implemented the refined algorithm in the IESA system developed for ETRI's smart card emulating system.