• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.377-381
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• 1990

In this paper, the stability analysis for the bilateral control of tele-manipulator is considered. Two-port network model is used to describe the tele-manipulator system. The stable conditions are derived using impedance matrix and passive network theory for two different types of bilateral control scheme. It is also shown that such conditions can be succefully applied to the n-d.o.f tele-manipulator system in which the kinematics and dynamics of master and slave manipulators are different.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.12
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• pp.1940-1946
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• 1989

A design method of lossy interstage networks for broadband microwave amplifiers is presented. A lossy interstage network is assumed as the combination of two lossless networks between which a lossy serial impedance or a lossy parallel admittance is inserted. For the circuit with two transistors and a lossy element, realizable ranges of gain and reflection coefficients are derived. And the relationships between gain and reflection coefficients are derived. Illustrative examples are presented by using the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.3
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• pp.166-172
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• 2004

Arc Fault Current is an electric discharge which is occurred in two opposite electrode. In this Paper, arc current control algorithm is designed for the interruption of arc fault current which is occurred in the low voltage network. This arc Is one of the main causes of electric fire. Arc fault in electrical network has the characteristics of low current, high impedance and high frequency. Conventional control algorithm does not have the arc current interrupt function. Hence, Control algorithm of arc current is designed for the interruption of arc fault current which has the modified arc characteristics.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.384-386
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• 2006

In this paper, arc current controller is designed for the interruption of arc fault current which is occurred in the low voltage network. Arc in electrical network have the characteristics of low current, high impedance and high frequency. Conventional controller does not have the arc current interrupt function. Hence, arc current controller is designed for the interruption of arc fault current.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1700-1701
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• 2007

DC Arc Fault Current is an electric discharge which is occurred in two opposite electrode. In this paper, DC arc detection device is designed for the display of DC arc fault current which is occurred in the local electric network with DC Power. This DC arc is one of the main causes of electric fire. Arc fault in electrical network has the characteristics of low current, high impedance and low frequency. DC Arc current detection device is designed for the display of arc fault current which has the modified arc characteristics.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.23-28
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• 2015

Two old synchronous condensers in Jeju are being replaced by new machines to operate Jeju AC network with Haenam-Jeju HVDC system stably. Before new synchronous condensers operate on site, voltage stability analysis is conducted to verify stable operation of jeju AC network. Through impedance analysis of the synchronous machine, transformer and ac network, the equivalent circuit is constructed and the voltage drop during start-up is calculated. Then, PSS/E fault analysis is performed to acquire short-circuit capacity according to the generator operation scenarios. Voltage variation when starting synchronous condenser is simulated in PSCAD/EMTDC and satisfies the operating condition of jeju AC network and HVDC #1 system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.49-60
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• 2002

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.985-991
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• 2000

In this paper, the optimum structure of 2GHz magnetic thin film planar inductor were designed and fabricated to reduce the inductor area and to maximize the inductance L and quality factor Q of the inductor. The optimum design was performed utilizing Co90Fe10 layer multilayered with SiO2 layers to avoid the eddy-current skin effect and considering new lumped element model. New magnetic thin film inductors operating at 2GHz were fabricated on a Si substrate utilizing photo-lithography and lift-off techniques. The frequency characteristics of L, Q, and impedance in more than fifty identical inductors were measured using an RF Impedance Analyzer(HP4291B with HP16193A test fixture). The self-resonant frequencies(SRF) of the inductors were measured by a Vector Network Analyzer(HP8510). The developed inductors have SRF of 1.8 to 2.3GHz, L of 47 to 68nH, and Q of 70 to 80 near 1GHz. Finally, high frequency, high performance, planar micro-inductor(area=30.8 x 30.8il$^2$) with maximized L and Q were fabricated succefully.

• Journal of electromagnetic engineering and science
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• v.18 no.2
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• pp.117-128
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• 2018

In this paper, compact linear dual polarized series-fed $1{\times}2$ linear and $2{\times}2$ planar arrays antennas for airborne SAR applications are proposed. The proposed antenna design consists of a square radiating patch that is placed on top of the substrate, a quarter wave transformer and $50-{\Omega}$ matched transformer. Matching between a radiating patch and the $50-{\Omega}$ microstrip line is accomplished through a direct coupled-feed technique with the help of an impedance inverter (${\lambda}/4$ impedance transformer) placed at both horizontal and vertical planes, in the case of the $2{\times}2$ planar array. The overall size for the prototype-1 and prototype-2 fabricated antennas are $1.9305{\times}0.9652{\times}0.05106{{\lambda}_0}^3$ and $1.9305{\times}1.9305{\times}0.05106{{\lambda}_0}^3$, respectively. The fabricated structure has been tested, and the experimental results are similar to the simulated ones. The CST MWS simulated and vector network analyzer measured reflection coefficient ($S_{11}$) results were compared, and they indicate that the proposed antenna prototype-1 yields the impedance bandwidth >140 MHz (9.56-9.72 GHz) defined by $S_{11}$<-10 dB with 1.43%, and $S_{21}$<-25 dB in the case of prototype-2 (9.58-9.74 GHz, $S_{11}$< -10 dB) >140 MHz for all the individual ports. The surface currents and the E- and H-field distributions were studied for a better understanding of the polarization mechanism. The measured results of the proposed dual polarized antenna were in accordance with the simulated analysis and showed good performance of the S-parameters and radiation patterns (co-pol and cross-pol), gain, efficiency, front-to-back ratio, half-power beam width) at the resonant frequency. With these features and its compact size, the proposed antenna will be suitable for X-band airborne synthetic aperture radar applications.

• Journal of IKEEE
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• v.25 no.4
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• pp.689-696
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• 2021

In this paper, in order to apply Prognostics and Health Management(PHM) to an electronic system or circuit, a circuit capable of detecting and predicting defect characteristics inside the system or circuit is implemented, and the results are described. In the previous study, we demonstrated that the frequency of the amplitude of S-parameter changed as the circuit defect progressed. These characteristics were measured by network analyser. but in this study, even if the same defect detection method is used, a circuit is proposed to check the progress of the defect, the remaining time, and the occurrence of the defect without large measurement devices. The circuit is designed to detect the change in impedance that generates changes of S-parameter, and it is verified through simulation using the measurement results of Bond-wires.