• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.369-375
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• 2010

This paper presents a design and implementation of 3.3 kW on-board battery charger for electric vehicles or plug-in hybrid electric vehicles. Considering characteristics of the electric vehicles, a series-loaded resonant dc-dc converter and frequency control scheme are adopted to improve efficiency and reliability, and to reduce volume and cost. The developed on-board battery charger is designed and implemented by using high frequency of 80-130 kHz and zero voltage switching method. The experimental result indicates 92.5% of the maximum efficiency, 5.84 liters in volume, and 5.8kg in weight through optimal hardware design.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.95-104
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• 1989

This paper presents a new shadow testing acceleration scheme for ray tracing called Hybrid Shadow Testing (HST) based on a conditional switching between the conventinal shadow testing method and Crow's shadow volume method, where the shadow polygons as well as the object polygons are registered onto the corresponding cells under the 3-D space subdivision environment. Despite the preprocessing time for the generation and registration of the shadow polygons, the total shadow testing time of the proposed algorithm, HST was approximately 50% of that of the conventional shadow testing method for several examples while the total ray tracing time was typically reduced by 30% from the conventional approach. This due to the selective use of the shadow volume method with a compromise between the maximal utilisation of shadow's spatial coherency and minimising the computational overhead for checking ray intersections with the shadow polygons. A parameter, $N_{th}$ denoting the critical number of shadow polygons between successive reflection points was used as a guideline for switching the shadow testing scheme between the conventional method and shadow volume method. A method for calculating $N_{th}$ from such statistical data as the number of object polygons, average polygon size average peripheral length of the polygons was proposed, resulting in good agreement with the experimental results.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.108-116
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• 2009

In this paper, we propose a Ethernet based audio distribution system with a new L1/L2 hybrid switching scheme, and evaluate its performance. The proposed scheme not only offers guaranteed low latency and jitter characteristics that are essentially required for the distribution of high-quality uncompressed audio traffic, and but also provide an efficient transmission of data traffic on the Ethernet environment. The audio distribution system with a proposed scheme consists of a master node and a number of relay nodes, and all nodes are mutually connected as a daisy-chain topology through up and downlinks. The master node generates an audio frame for each cycle of 125us, and the audio frame has 24 time slotted audio channels for carrying stereo 24 channels of 16-bit PCM sampled audio. On receiving the audio frame from its upstream node via the downlink, each intermediate node inserts its audio traffic to the reserved time slot for itself, then relays again to next node through its physical layer(L1) transmission - repeating. After reaching the end node, the audio frame is loopbacked through the uplink. On repeating through the uplink, each node makes a copy of audio slot that node has to receive, then play the audio. When the audio transmission is completed, each node works as a normal L2 switch, thus data frames are switched during the remaining period. For supporting this L1/L2 hybrid switching capability, we insert a glue logic for parsing and multiplexing audio and data frames at MII(Media Independent Interlace) between the physical and data link layers. The proposed scheme can provide a good delay performance and transmission efficiency than legacy Ethernet based audio distribution systems. For verifying the feasibility of the proposed L1/L2 hybrid switching scheme, we use OMNeT++ as a simulation tool with various parameters. From the simulation results, one can find that the proposed scheme can provides outstanding characteristics in terms of both jitter characteristic for audio traffic and transmission efficiency of data traffics.

• Journal of Power Electronics
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• v.18 no.2
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• pp.558-572
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• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.

• Journal of Advanced Navigation Technology
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• v.26 no.1
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• pp.35-45
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• 2022

In this paper, we modeled the devices used easily in PV system circuits. In addition, for full operation of the photovoltaic system, a complete operation system for the DC-DC buck-boost converter and the MPPT control system was modeled and simulated to confirm good operation. we were constructed an actual system with the same conditions in the simulation and experimented. The purpose is to confirm the stable power supply through the load leveling by presenting the PCS considering ESS of photovoltaic power generation. we will do study to apply hybrid capacitors that have high energy density to the same size compared to the EDLC to DVR. As a result, we proposed a single-phase 3 kW grid-connected solar power converter.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.10
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• pp.2509-2528
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• 2012

Time division multiple access (TDMA) is a widely used media access control (MAC) technique that can provide collision-free and reliable communications, save energy and bound the delay of packets. In TDMA, energy saving is usually achieved by switching the nodes' radio off when such nodes are not engaged. However, the frequent switching of the radio's state not only wastes energy, but also increases end-to-end delay. To achieve high energy efficiency and low delay, as well as to further minimize the number of time slots, a multi-objective TDMA scheduling problem for industrial wireless mesh networks is presented. A hybrid algorithm that combines genetic algorithm (GA) and simulated annealing (SA) algorithm is then proposed to solve the TDMA scheduling problem effectively. A number of critical techniques are also adopted to reduce energy consumption and to shorten end-to-end delay further. Simulation results with different kinds of networks demonstrate that the proposed algorithm outperforms traditional scheduling algorithms in terms of addressing the problems of energy consumption and end-to-end delay, thus satisfying the demands of industrial wireless mesh networks.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.5
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• pp.373-380
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• 2016

In this paper, a 50-kW high-efficiency modular fast charger for both electric vehicle (EV) and neighborhood electric vehicle (NEV) is proposed. The proposed fast charger consists of five 10-kW modules to achieve fault tolerance, ease of thermal management, and reduce component stress. Three-level topologies for both AC-DC and DC-DC converters are employed to use 600V MOSFET, resulting in ease of component selection and increase in switching frequency. The proposed three-level DC-DC converter with coupled inductor and its hybrid switching method can reduce the circulating current under wide output voltage range. A 50-kW prototype of the proposed fast charger was developed and tested to verify the validity of the proposed concept. Experimental results show that the proposed fast charger achieves a rated efficiency of 95.2% and a THD of less than 3%.