• Journal of the Korean Ceramic Society
• /
• v.50 no.3
• /
• pp.238-243
• /
• 2013

We investigated the effect of Pb-metal filler added to a hybrid paste(PbO-$Bi_2O_3-B_2O_3$-ZnO glass frit and Pb-powder), for joining flip-chip sat lower temperatures than normal. The glass transition temperature was detected at $250^{\circ}C$ and the softening point occurred at $330^{\circ}C$. As the temperature increased, the specific density decreased due to the volatility of the Pb-metal and boron component in the glass. When the glass was heat-treated at $350^{\circ}C$ for 5 min, XRD results revealed a crystalline $Pb_4Bi_3B_7O_{19}$ phase that had been initiated by the addition of Pb-filler in the hybrid paste. The addition of the Pb-metal filler caused are action between the Pb-metal and glass that accelerated the formation of the liquid phase. The liquid phase that formed, promoted bonding between the flip-chip substrate sat lower temperature.

• Journal of KIISE
• /
• v.42 no.2
• /
• pp.183-189
• /
• 2015

Recently, computer systems have encountered difficulties in making further progress due to the technical limitations of DRAM based main memory technologies. This has motivated the development of next generation memory technologies that have high density and non-volatility. However, these new memory technologies also have their own intrinsic limitations, making it difficult for them to currently be used as main memory. In order to overcome these problems, we propose a hybrid main memory system, namely HyMN, which utilizes the merits of next generation memory technologies by combining two types of memory: Write-Affable RAM(WAM) and Read-Affable RAM(ReAM). In so doing, we analyze the appropriate WAM size for HyMN, at which we can avoid the performance degradation. Further, we show that the execution time performance of HyMN, which provides an additional benefit of durability against unexpected blackouts, is almost comparable to legacy DRAM systems under normal operations.

• Journal of Digital Contents Society
• /
• v.11 no.1
• /
• pp.91-97
• /
• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• Journal of KIISE
• /
• v.42 no.8
• /
• pp.947-953
• /
• 2015

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.

• Proceedings of the Polymer Society of Korea Conference
• /
• 2006.10a
• /
• pp.370-370
• /
• 2006

Thermoplastic elastomer gels, which has molecular networks composed of a microphase-separated multiblock copolymer swollen to a large extent by a low volatility mid-block selective solvent such as white oil have various applications. In this particular study, the effect of several network-forming nanoscale fillers such as two different graphite particles and carbon nanotube on the properties of TPE gels prepared from a microphaseordered poly[styrene-b-(ethylene-co-butylene)-b-styrene] (SEBS) triblock copolymer with an EB compatible white oil was studied. The linear viscoelastic behavior, sol-gel transition, x-ray diffraction and mechanical properties were discussed. The properties of thermoplastic elastomer gels hybrid with graphite prepared by mixing Poly(styrene-b-ethylene-co-butylene)-b-styrene) with paraffin oil and different amount of expandable graphite were found to increase the mechanical properties at only lower graphite concentration but tends to decrease when paraffin oil/SEBS ratio is lower. The gelation temperature is the same for all TPE gels with different amounts of graphite. Both storage (G') modulus loss (G") modulus of TPE gels slightly increase with addition of graphite.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.12
• /
• pp.4997-5006
• /
• 2010

A flash-memory-based SSDs(Solid State Disks) are one of the best media to support portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major database storage components for desktop and server computers. However, we need to improve traditional storage management schemes based on HDD(Hard Disk Drive) and RAID(Redundant array of independent disks) due to the relatively slow or freezing characteristics of write operations of SSDs, as compared to fast read operations. In order to achieve this goal, we propose a new storage management scheme called Hetero-Mirroring based on traditional HDD mirroring scheme. Hetero-Mirroring-based scheme improves RAID-1 operation performance by balancing write-workloads and delaying write operations to avoid SSD freezing. Our test results show that our scheme significantly reduces the write operation overheads and freezing overheads, and improves the performance of traditional SSD-RAID-1 scheme by 18 percent, and the response time of the scheme by 38 percent.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.5
• /
• pp.1354-1358
• /
• 2008

Environmental-friendly nontocxic flame retardant paint which can overcomes the restriction of harmful materials for human body and environments such as Pb, Hg, Cd, $C^{+6}$, PBB/PBDE by EU and domestic Ministry of Environment was developed. Developed paint is the water-soluble organic inorganic hybrid material that VOC(volatility organic compound) discharge is low, and that human riskiness and environmental pollution is minimized not using the kinds of halogen materials. $Mg(OH)_2$, $Sb_{2}O_{3}$, and Zinc borate were used as flame retardant materials, 2% Micell and water were used as binder and solvent, respectively. Results showed the optimum activity was obtained when the ratio of those frame retardant agents($Mg(OH)_2$, $Sb_{2}O_{3}$, Zinc borate made by 1: 2: 2), binder(2% Micell) and water was 1: 0.5: 0.5.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.2
• /
• pp.111-124
• /
• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.