• Title/Summary/Keyword: hybrid redundancy

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A Hybrid Decoding Algorithm for MPE-FEC based on DVB-SSP (DVB-SSP 기반 혼합형 MPE-FEC 복호 알고리즘)

  • Park, Tae-Doo;Kim, Min-Hyuk;Kim, Nam-Soo;Kim, Chul-Sung;Jung, Ji-Won;Lee, Seong-Ro
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.9C
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    • pp.848-854
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    • 2009
  • DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handhold systems and fixed terrestrial systems. An upper layer, including erasure Reed-Solomon error correction combined with cyclic redundancy check. However, a critical factor must be considered in upper layer decoding. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. If, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed upper layer decoding methods; hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one in AWGN channel and TI channel.

Design Space Exploration of EEPROM-SRAM Hybrid Non-volatile Counter Considering Energy Consumption and Memory Endurance (에너지 소비 및 메모리 내구성을 고려한 EEPROM-SRAM 하이브리드 비휘발성 카운터의 설계 공간 탐색)

  • Shin, Donghwa
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.4
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    • pp.201-208
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    • 2016
  • Non-volatile counter is a counter that maintains the value without external power supply. It has been used for the applications related to warranty issues to count and record certain events such as power cycles, operating time, hard resets, and timeouts. It has been conventionally implemented with volatile memory-based counter and battery backup or non-volatile memory such as EEPROM. Both of them have a lifetime issue due to the limited lifetime of the battery and the endurance of the non-volatile memory cells, which incurs significant redundancy in design. In this paper, we introduce a hybrid architecture of volatile (SRAM) and non-volatile memory (EEPROM) cells to achieve required lifetime of the non-volatile counter with smaller cost. We conduct a design space exploration of the proposed hybrid architecture with the parameters of various kinds of non-volatile memories. The analysis result shows that the proposed hybrid non-volatile counter can extend the lifetime up to 6 times compared to the battery-backup volatile memory-based implementation.

Network Anomaly Detection using Hybrid Feature Selection

  • Kim Eun-Hye;Kim Se-Hun
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 2006.06a
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    • pp.649-653
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    • 2006
  • In this paper, we propose a hybrid feature extraction method in which Principal Components Analysis is combined with optimized k-Means clustering technique. Our approach hierarchically reduces the redundancy of features with high explanation in principal components analysis for choosing a good subset of features critical to improve the performance of classifiers. Based on this result, we evaluate the performance of intrusion detection by using Support Vector Machine and a nonparametric approach based on k-Nearest Neighbor over data sets with reduced features. The Experiment results with KDD Cup 1999 dataset show several advantages in terms of computational complexity and our method achieves significant detection rate which shows possibility of detecting successfully attacks.

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CRC-Turbo Concatenated Code for Hybrid ARQ System

  • Kim, Woo-Tae;Kim, Jeong-Goo;Joo, Eon-Kyeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3C
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    • pp.195-204
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    • 2007
  • The cyclic redundancy check(CRC) code used to decide retransmission request in hybrid automatic repeat request(HRAQ) system can also be used to stop iterative decoding of turbo code if it is used as an error correcting code(ECC) of HARQ system. Thus a scheme to use CRC code for both iteration stop and repeat request in the HARQ system with turbo code based on the standard of cdma 2000 system is proposed in this paper. At first, the optimum CRC code which has the minimum length without performance degradation due to undetected errors is found. And the most appropriate turbo encoder structure is also suggested. As results, it is shown that at least 32-bit CRC code should be used and a turbo code with 3 constituent encoders is considered to be the most appropriate one.

Compliant motion controllers for kinematically redundant manipulators

  • Park, Jonghoon;Chung, Wan-Kyun;Youm, Youngil
    • 제어로봇시스템학회:학술대회논문집
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    • 1995.10a
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    • pp.456-459
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    • 1995
  • The problem of compliant motion control using a redundant manipulator is addressed in this article. Specifically, a hybrid-control type and impedance-control type controllers are extended to general redundant manipulators based on the kinematically decomposed and geometrically compatible modeling of its joint space. In the case of the hybrid controller, it leads to the linear and decoupled closed-loop dynamics in the three motion spaces, that is the motion-controlled, force-controlled, and the null motion-controlled spaces of the redundant manipulator. When the proposed impedance controller is applied, the decoupled impedance models in three motion spaces are obtained. The superiority of the proposed controllers is verified with the numerical experiments.

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Quasi-Complementary Turbo Codes (QCTC) for cdma2000 1xEV-DV

  • Kim, Min-Goo;Ha, Sang-Hyuk;Kim, Yong-Serk
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.97-100
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    • 2003
  • The quasi-complementary turbo codes (QCTC) proposed by Kim [1] is used for a fast hybrid ARQ scheme with incremental redundancy and adaptive modulation coding in the cdma2000 1xEV-DV [2]. The QCTC provides various code rates with good performance, a very simple encoder structure, and an inherent channel interleaving. It is shown that the QCTC is a unified scheme of channel coding and channel interleaving. In this paper, we introduce the properties of QCTC and various hybrid ARQ-QCTC schemes for the system.

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Error-detection-coding-aided iterative hard decision interference cancellation for MIMO systems with HARQ

  • Park, Sangjoon
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.3
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    • pp.1016-1030
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    • 2018
  • In this paper, an error-detection-coding-aided iterative hard decision interference cancellation (EDC-IHIC) scheme for multiple-input multiple-output systems employing hybrid automatic repeat request (HARQ) for multi-packet transmission is developed and investigated. In the EDC-IHIC scheme, only packets identified as error-free by the EDC are submitted to the interference cancellation (IC) stage for cancellation from the received signals. Therefore, the possibility of error propagation, including inter-transmission error propagation, can be eliminated using EDC-IHIC. Because EDC must be implemented in systems that employ HARQ to determine packet retransmission, error propagation can be prevented without the need for additional redundancy. The results of simulations conducted herein verify that the EDC-IHIC scheme outperforms conventional hard decision IC schemes in terms of the packet error rate in various environments.

Hybrid Multiple Description Video Coding Using SD/MD Switching (SD/MD 전환을 이용한 하이브리드 다중 표현 동영상 압축 방법)

  • Kim Il Koo;Cho Nam Ik
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2003.11a
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    • pp.27-30
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    • 2003
  • 본 논문에서는 하이브리드 다중 표현(hybrid multiple description) 개념을 이용하여 에러가 발생하기 쉬운 환경에서 사용될 수 있는 강인한 동영상 압축 알고리듬을 제안한다. 다중 표현 압축은 단일 표현 압축(single description coding. SDC) 보다 패킷 손실 율(packet loss rate, PLR)이 높은 환경에서 에러에 더 강인성을 갖는다. 그러나 PLR 이 낮은 환경에서는 과도한 중복량(redundancy) 때문에 성능이 저하되는 문제가 발생한다 이러한 MDC 의 문제를 해결하기 위해서 채널 환경에 따라 SD/MID 를 전환할 수 있는 방법을 제안한다. 좀더 자세히 설명하면, 낮은 PLR 에서는 압축 효율을 위하여 SDC 를 사용하고 높은 PLR 환경에서는 에러에 대한 강인성을 위해 MDC 를 사용한다. SD/MD 전환을 최적화시키기 위해 비트율-왜곡 최적화 프레임웍(rate-distortion optimization framework)을 사용한다. 부호화시에 복호기에서의 왜곡(distortion)을 정확히 예측하기 위해서 ROPE(recursive optimal per-pixel estimate) 방법을 사용한다. 모의 실험 견과 제안된 SD/MD 전환 방법이 기존의 SDC-ROPE 와 MDC-ROPE 보다 모든 에러 환경에서 더 효과적임을 알 수 있다.

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Direct displacement based design of hybrid passive resistive truss girder frames

  • Shaghaghian, Amir Hamzeh;Dehkordi, Morteza Raissi;Eghbali, Mahdi
    • Steel and Composite Structures
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    • v.28 no.6
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    • pp.691-708
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    • 2018
  • An innovative Hybrid Passive Resistive configuration for Truss Girder Frames (HPR-TGFs) is introduced in the present study. The proposed system is principally consisting of Fluid Viscous Dampers (FVDs) and Buckling Restrained Braces (BRBs) as its seismic resistive components. Concurrent utilization of these devices will develop an efficient energy dissipating mechanism which is able to mitigate lateral displacements as well as the base shear, simultaneously. However, under certain circumstances which the presence of FVDs might not be essential, the proposed configuration has the potential to incorporate double BRBs in order to achieve the redundancy of alternative load bearing paths. This study is extending the modern Direct Displacement Based Design (DDBD) procedure as the design methodology for HPR-TGF systems. Based on a series of nonlinear time history analysis, it is demonstrated that the design outcomes are almost identical to the pre-assumed design criteria. This implies that the ultimate characteristics of HPR-TGFs such as lateral stiffness and inter-story drifts are well-proportioned through the proposed design procedure.

Dual Vector Control Strategy for a Three-Stage Hybrid Cascaded Multilevel Inverter

  • Kadir, Mohamad N. Abdul;Mekhilef, Saad;Ping, Hew Wooi
    • Journal of Power Electronics
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    • v.10 no.2
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    • pp.155-164
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    • 2010
  • This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.