• 전자공학회논문지C
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• 제34C권5호
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• pp.19-32
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• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.107-116
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• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2020년도 추계학술발표대회
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• pp.20-23
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• 2020

This research is to design an effective prefetching method required for DRAM-PCM hybrid main memory systems especially used for big data applications and massive-scale computing environment. Conventional prefetchers perform well with regular memory access patterns. However, workloads such as graph processing show extremely irregular memory access characteristics and thus could not be prefetched accurately. Therefore, this research proposes an efficient dynamical prefetching algorithm based on the regression method. We have designed an intelligent prefetch engine that can identify the characteristics of the memory access sequences. It can perform regular, linear regression or polynomial regression predictive analysis based on the memory access sequences' characteristics, and dynamically determine the number of pages required for prefetching. Besides, we also present a DRAM-PCM hybrid memory structure, which can reduce the energy cost and solve the conventional DRAM memory system's thermal problem. Experiment result shows that the performance has increased by 40%, compared with the conventional DRAM memory structure.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2020년도 추계학술발표대회
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• pp.12-15
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• 2020

Data access characteristics can directly affect the efficiency of the system execution. This research is to design an accurate predictor by using historical memory access information, where highly accessible data can be migrated from low-speed storage (SSD/HHD) to high-speed memory (Memory/CPU Cache) in advance, thereby reducing data access latency and further improving overall performance. For this goal, we design a locally weighted linear regression prefetch scheme to cope with irregular access patterns in large graph processing applications for a DARM-PCM hybrid memory structure. By analyzing the testing result, the appropriate structural parameters can be selected, which greatly improves the cache prefetching performance, resulting in overall performance improvement.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• IEIE Transactions on Smart Processing and Computing
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• 제5권4호
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• pp.274-282
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• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• Structural Engineering and Mechanics
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• 제53권5호
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• pp.1031-1049
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• 2015

This paper highlights the role of innovative vibration control system based on two promising properties in a parallel configuration. Hybrid device consists of two main components; recentering wires of shape memory alloy (SMA) and steel pipe section as an energy dissipater element. This approach concentrates damage in the steel pipe and prevents the main structural members from yielding. By regulation of the main adjustable design parameter, an optimum performance of the device is obtained. The effectiveness of the device in passive control of structures is evaluated through nonlinear time history analyses of a five-story steel frame with and without the hybrid device. Comparing the results proves that the hybrid device has a considerable potential to mitigate the residual drift ratio, peak absolute acceleration and peak interstory drift of the structure.

• International Journal of Internet, Broadcasting and Communication
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• 제12권1호
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• pp.90-94
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• 2020

Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially, MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.

• 정보과학회 논문지
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• 제42권2호
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• pp.183-189
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• 2015

최근 DRAM 기반의 메인 메모리 기술 발전이 한계에 봉착함에 따라 컴퓨터 시스템의 진보에도 어려움이 발생하고 있다. 이를 개선하기 위해 집적도가 높고 비휘발성을 갖는 차세대 메모리 기술이 등장하고 있으나 이들은 쓰기 속도가 느리거나 쓰기 횟수에 제한이 있는 등, 메인 메모리로 사용하기에는 아직 무리가 있다. 본 논문에서는 여러 차세대 메모리 기술들의 장점들을 조합하여 활용하는 하이브리드 메인 메모리 시스템, 즉 HyMN을 제안한다. HyMN은 차세대 메모리 기술을 쓰기적합램과 읽기적합램으로 분류하여 메인 메모리 시스템을 구성함으로써, 내구성이 양호하고, 고용량화가 용이하며, 비휘발성을 활용할 수 있는 시스템을 구현한다. 본 논문에서는 또한, 쓰기적합램이 어느 정도의 크기로 구성되어야 하는지를 보이고 정전 시 손실에 대한 복구비용이 없거나 미미한 HyMN이 일상적으로 프로세스를 실행할 때 실행 시간 성능이 DRAM으로만 구성된 시스템에 비하여 유사함을 검증한다.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.65-70
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• 2024

Direct cache-to-cache transfer has been studied to reduce the latency and bandwidth consumption related to the shared data in multiprocessor system. Even though these studies lead to meaningful results, they assume that caches consist of SRAM. For example, if the system employs the non-volatile memory, the one of the most important parts to consider is to decrease the number of write operations. This paper proposes a hybrid write avoidance cache coherence protocol that considers the hybrid cache architecture. A new state is added to finely control what is stored in the non-volatile memory area, and experimental results showed that the number of writes was reduced by about 36% compared to the existing schemes.