• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.73-76
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• 2001

A key requirement for packet based wireless communication systems is to provide a high data rate packet service and improved throughput. To achieve a high throughput, adaptive methods for adjustment of the modulation and coding can be used. In this paper, we propose and analyze a scheme which is a combination of an adaptive modulation and coding(AMC) and transmit diversity(TD). Two different TD schemes are analysed: STTD and STD. Proposed system provides significant improvement in the average throughput.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1982.10a
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• pp.37-39
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• 1982

In this paper, we deal with theoretical tools to improve the throughput efficiency of the conventional Go-Back-N ARQ system by performing block retransmission efficiently under high error rate, and two variations of the system is proposed.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.23.2-23.2
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• 2009

Atomic layer deposition (ALD)have been proven to be a very attractive technique for the fabrication of advanced gate dielectrics and DRAM insulators due to excellent conformality and precise control of film thickness and composition, However, one major disadvantages of ALD is its relatively low deposition rate (throughput) because the deposition rate is typically limited by the time required for purging process between the introduction of precursors. In order to improve its throughput, many efforts have been made by commercial companies, for example,the modification reactor and development of precursors. However, any promising solution has not reported to date. We developed a new concept ALD system(Lucida TM S200) with high-throughput. In this process, a continuous flow of ALD precursor and purging gas are simultaneously introduced from different locations in the ALD reactor. A cyclic ALD process is carried out by moving the wafer holder up and down. Therefore, the time required for ALD reaction cycle is determined by speed of the wafer holder and vapor pressure of precursors. We will present the operating principle of our system and results of deposition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9A
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• pp.924-933
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• 2008

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5B
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• pp.270-276
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• 2007

The proposed LDS(Link-status Dependent Scheduling) algorithm in HR-WPAN(High Rate-Wireless Personal Area Network) up to now aims at doing only throughput elevation of the whole network, when the crucial device is connected with worst-link relatively, throughput of this device becomes aggravation. The proposed the WGS(Worst-case Guaranteed Scheduling) algorithm in this paper guarantees throughput of the device which is connected with worst-link in a certain degree as maintaining throughput of all devices identically even if a link-status changes, decreases delay of the whole network more than current LDS algorithm. Therefore proposed WGS algorithm in this paper will be useful in case of guaranteeing throughput of a device which is connected worst-link in a certain degree in a design of HR-WPAN hereafter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.254-266
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• 2006

Recently, researches about downlink resource allocation algorithms applying SDMA to enhance the system throughput and cell coverage have begun. Most OFDM/SDMA based resource allocation algorithms have some limitations such that those only concentrate on maximizing the system throughput or can be applied in single cell environment. In this paper, we propose an OFDM/SDMA based downlink resource allocation algorithm which considers high layer QoS parameters suitable for the required data traffic and it also minimizes the system throughput loss and considers inter-cell interference from adjacent cells. so it can be adopted in multi-cell environment. We manifest the performance of the proposed algorithm in Ped A and SCME MIMO Channel Model.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.100-104
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• 2020

Thus far, several in vivo biosensing platforms have been proposed to measure the mechanical contractility of cultured cardiomyocytes. However, the low sensitivity and screening rate of the developed sensors severely limit their practical applications. In addition, intensive research and development in cardiovascular disease demand a high-throughput drug-screening platform based on biomimetic engineering. To overcome the drawbacks of the current state-of-the-art methods, we propose a high-throughput drug-screening platform based on 16 functional high-sensitivity well plates. The proposed system simulates the physiological accuracy of the heart function in an in vitro environment. We fabricated 64 cantilevers using highly flexible and optically transparent silicone rubber and placed in 16 independent wells. Nanogrooves were imprinted on the surface of the cantilever to promote cell alignment and maturation. The adverse effects of the cardiovascular drugs on the cultured cardiomyocytes were systematically investigated. The 64 cantilevers demonstrated a highly reliable and reproducible mechanical contractility of the drug-treated cardiomyocytes. Real-time high-throughput screening and simultaneous evaluation of the cardiomyocyte mechanical contractility under multiple drugs verified that the proposed system could be used as an efficient drugtoxicity test platform.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1168-1170
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• 2008

For OLED to be a key role in the television market, a manufacturing evaporation system with robustness and high throughput is indispensable. ANS is currently developing manufacturing equipments for OLED TVs. ANS's latest progress of a vertical high throughput in-line evaporation system for large substrate will be presented.