• Proceedings of the KSR Conference
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• 1998.05a
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• pp.233-240
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• 1998

In the design of the high-speed railway vehicles of low noise and vibration characteristics, it is desirable to develop efficient and systematic procedures for analyzing large structures. In this paper, some finite-element modelling techniques and an efficient analytical method are proposed for this purpose. The analytical method is based on substructuring approach such as a free-interface method and a generalized synthesis algorithm. In final, the proposed approaches are applied to the finite-element modelling, modal analysis and subsequent model updating procedures of the high-speed railway intermediate trailers.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.149-158
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• 1994

Through high level synthesis, designers can obtain the precious information on the area and speed trade-offs as well as synthesized datapaths from behavioral design descriptions. While previous researches were concentrated on the synthesis of pipelined, datapaths with fixed DII (Data Initiation Interval) by inserting delay elements where needed, we propose a novel methodology of synthesizing pipeline structures with variable DIIs. Determining the time-overlapping of pipeline stages with variable DIIs, the proosed algorithm performs scheduling and module allocation using the time-overlapping information. Experimental results show that significant improvement can be achieved both in speed and in area.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.176-179
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• 2000

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in current digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator systemfor for digital image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.443-447
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• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.284-287
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• 2001

In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.333-339
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• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5416-5426
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• 2012

This study uses the algorithm which estimates the magnetic flux using different models in the low speed driving area and the high speed driving area by the voltage-current model synthesis magnetic flux Estimator and, from this result, estimates the magnetic flux angle to achieve the stable speed control through all the areas from the low speed to the high speed drive. In particular, the current change and the magnetic flux change under variable load were estimated in real time in the low speed area and this made the control characteristic improved in the low speed area. According to this, even under variable load, the more stable simulation and experiment could have been completed using PI current controller and PI flux controller in all the areas. As a result, the outstanding speed control characteristic has been achieved.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.1
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• pp.33-49
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• 1995

Simulated annealing(SA) has been admitted as a general purpose optimization technique which can be utilized for almost all kinds of combinatorial optimization problems without much difficulty. But there are still some weak points to be resolved, one of which is the slow speed of convergence. In this study, we carefully review various previous efforts to improve SA and propose some variations of SA which can enhance the speed of convergence to the optimum solution. Then, we apply the revised SA algorithms to the scheduling and hardware allocation problems occurring in high-level synthesis(HLS) of VLSI design. We confirm the efficiency of the proposed methods through several HLS examples.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Journal of the Korean Ceramic Society
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• v.28 no.3
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• pp.234-242
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• 1991

Ti-B system ceramics were prepared by the self-propagating high-temperature synthesis method from the mixture of metal titanium and boron powders The major crystalline phase as a function of boron content was TiB for mixtures containing 0.5 or 1.0mol B, and TiB2 for these containing over 1.3mol B. The combustion mode observed by a high-speed camera was steady-state. The Combustion velocity increased with increasing the boron content. Sintered TiB2 specimen showed the density of 97% of theoretical valve, Vicker's hardness of 2250kg/㎟ for 0.2kg load and three-point-flexure strength of 500MPa.