• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.55-65
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• 2004

ATM was recommended by the ITU and ATM Forum as a means of transportation for B-ISDN. At this time, due to the comprehensive mature of ATM protocol, ATM has been adapted as the backbone system for carrying Internet traffi $c^{[1,2,3,4]}$. But major conceptsregarding the ATN protocol will be used on future technology. This paper presents preventive congestion control mechanisms for detecting HTR(Hard-To Reach) code in ATM systems, in particular for an improved HTR call registration method using network signaling information will discussed. In high speed circuit switching system environments, a fast HTR control mechanism is necessary. We present research results for improving HTR call registration and control methods using network signaling information and fuzzy control mechanisms. We concluded that it showed fast congestion avoidance mechanisms with a fewer system load maximized the efficiency of network resources by restricting ineffective machine attempts.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.979-982
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• 2003

Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.1223-1228
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• 2007

Since KHSL 2nd phase was adapted as a main track design, the interests of concrete slab track system have been gradually increased in the division of rail track engineering and many engineering companies have been trying to adapt a concrete slab track system at this moment. Advantages of this system proved in advanced country, japan and Germany etc. are excellent maintenance, track stability and increasing of buckling resistance This developed turnout is same with the KHSR 1st phase's design and applications rules, components and signaling system since it observes KTX specification. Comparing it with the former turnout, High-elasticity pad, lubrication-free roller slide plate and Rheda2000 PC sleeper are only different. The purpose of this study is the development of high speed turnout on concrete slab track and its application on site. Now these studies are going to show the verification and confidence about the interface between ballast-track and concrete slab track by finding and solving the possible problems when it is installed on site and to make these turnouts applied perfectly and completely on concrete slab track. Its first trial construction in korea had been successfully completed at Sangju-station on July 20th ,2007 thanks to KORAIL and KR. Hereunder Sampyo E&C trys to introduce all of turnout technologies on concrete slab track system with Rheda 2000 sleeper

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.2 no.4
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• pp.171-183
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• 2008

Nowadays, wireless packet data services are provided over Wireless MAN (WMAN) at a high data service rate, while 3G cellular networks provide wide-area coverage at a low data service rate. The integration of mobile WiMAX and 3G networks is essential, to serve users requiring both high-speed wireless access as well as wide-area connectivity. In this paper, we propose a cross-layer optimization scheme for a vertical handover between mobile WiMAX and 3G cellular networks. More specifically, L2 (layer 2) and L3 (layer 3) signaling messages for a vertical handover are analyzed and reordered/combined, to optimize the handover procedure. Extensive simulations using ns-2 demonstrate that the proposed scheme enhances the performance of a vertical handover between mobile WiMAX and 3G networks: low handover latency, high TCP throughput, and low UDP packet loss ratio.

• ETRI Journal
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• v.35 no.5
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• pp.827-837
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• 2013

In this paper, we present wideband common-mode (CM) noise suppression using a vertical stepped impedance electromagnetic bandgap (VSI-EBG) structure for high-speed differential signals in multilayer printed circuit boards. This technique is an original design that enables us to apply the VSI-EBG structure to differential signals without sacrificing the differential characteristics. In addition, the analytical dispersion equations for the bandgap prediction of the CM propagation in the VSIEBG structure are extracted, and the closed-form expressions for the bandgap cutoff frequencies are derived. Based on the dispersion equations, the effects of the impedance ratio, the EBG patch length, and via inductances on the bandgap of the VSI-EBG structure for differential signals are thoroughly examined. The proposed dispersion equations are verified through agreement with the full-wave simulation results. It is experimentally demonstrated that the proposed VSI-EBG structure for differential signaling suppresses the CM noise in the wideband frequency range without degrading the differential characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.761-764
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• 2007

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and πace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1618-1625
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• 2015

The reliability of catenary system is very important for uninterrupted train operation as it supplies electric power to train without redundant facilities. This paper provides a systematic approach to the reliability analysis of the catenary system based on FMECA procedures defined by global standards such as MIL Std 1692a and IEC 60812. Field failure data collected from the operation and maintenance of high-speed railway catenary system for 9 years are used to derive critical failure modes and to evaluate the criticality of the failure modes. Evaluation of the criticality are carried out by quantitative procedures defined by MIL Std 1692a and by criticality matrix defined by IEC 60812. FMECA results suggests that three critical failure modes should be checked carefully during maintenance work, which include strand break of dropper and voltage equalizing wire, power supply failure of feeder. Maintenance procedure of catenary system in order of importance is suggested too. These results can be applied to maintenance planning and design of catenary system to improve the reliability of electric railway system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.522-525
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• 2006

Recently, mobile devices support multi-functions such as 3D game, wireless internet, moving pictures, DMB, GPS, and PMP. Bigger size of display device is indispensable to support these functions and higher speed of the interface is needed. However, conventional parallel interfaces between processor and display nodule are not competent enough for that high speed transfers. High-speed serial interface is beginning to appear as an alternative for parallel interface. The advantages of the serial interface are high bandwidth, small number of interconnections, low-power consumption, and good quality of electro-magnetic interference. In this paper, we implement serial interface and use it for a display module. LVDS is used for PHY layer and a defined packet is used for link layer. The feature of the implemented serial interface is the reduced number of interconnections with enough bandwidth.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1379-1385
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• 2009

We propose a low-power and high-speed client receiver for a mobile display digital interface (MDDI) newly in this paper. The low-power receiver is designed such that bias currents, sink and source currents, are insensitive to variations of power supply, process, temperature, and common-mode input voltage (VCM) and is able to operate at a rate of 450Mbps or above under the conditions of a power supply range of 3.0 to 3.6Vand a temperature range of -40 to 85$^{\circ}$C. And it is confirmed by a simulation result that the current dissipation is less than 500${\mu}$A. A test chip is manufactured with the Magna chip 0.35${\mu}$m CMOS process. When a test was done, the data receiver and data recovery circuits are functioning normally.