• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.336-339
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• 1999

In this paper, we describe the accommodation of the PRML technique for the high speed and high density optical disk systems, which has been very effective in the high density HDD systems. To make the PRML technique adequate for the optical disk systems, the channel modeling and the simulation are performed. Finally, the architecture has been designed and realized into an ASIC. We have focused on the differences of PRML architecture between the HDD system and the optical disk system, and the digital realization of the PLL which has been realized with analog circuits.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2000년도 추계학술대회논문집 - 한국공작기계학회
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• pp.32-37
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• 2000

In a high speed spindle system, it is very important to monitor the operation of the spindle to prevent catastrophic damage to the system. Widely used sensors for monitoring are eddy-current and capacitive types. These sensors provide high accuracy of monitoring, but their steep prices lead to expensive high speed spindle system. The main god of our research is to develop technology to produce high speed spindle system utilizing magnetic bearings. As active magnetic bearings require position sensors for feedback control, a noncontact position sensor is bang developed as a part of this main goal. Once developed, it will contribute to affordable high speed spindle system. In this paper, we report the selection process of the sensor types and the experimental results with driving circuits.

• 대한기계학회논문집A
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• 제32권11호
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• pp.943-950
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• 2008

A novel nondestructive testing (NDT) system, which is able to detect a crack with high speed and high spatial resolution, is urgently required for inspecting small cracks on express train wheels. This paper proposes a high speed scan type magnetic camera, which uses the multiple amplifying circuits and the crack indicating pulse output system. The linearly integrated Hall sensors are arrayed in parallel, and the Hall voltages from each sensor in the scanning direction are obtained and amplified. High-speed NDT can be achieved by using the exclusive analog-digital converter and micro-processor because the ${\partial}\;V_H/\;{\partial}$ x value, which provides the most important crack information, can be obtained by buffering and calculating. The effectiveness of the novel method was verified by examine using cracks on the wheel specimen model.

• 한국정보처리학회논문지
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• 제4권1호
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• pp.298-310
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• 1997

스캔 환경에 바탕을 둔 대부분의 경로 지연고장 시뮬레이터들은 개선된 스캔 플 립플롭을 사용하며 일반적인 논리 게이트를 대상으로만 동작한다. 본 연구에서는 새 로운 논리값을 사용한 새로운 경로 지연고장 시뮬레이션 알고리즘을 고안하여 이의 적용범위를 CMOS 소자를 포함하는 대규모 집적회로로 확장하였다. 제안된 알고리즘에 기초하여 표준 스캔 환경 하에서 동작하는 고속 지연고장 시뮬레이터를 개발하였다. 실험결과는 새 시뮬레이터가 효율적이며 정확함을 보여준다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.863-866
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• 1998

In this paper two quick boosting charge pump circuits for high-speed EEPROM memory are proposed. In order to improve initial charge transfer efficiency, one uses weighted capacitors where each stage has different clock coupling capacitance, and the other uses a multi-path structure at the first stage. SPICE simulation results show that these charge pumps have improve drising-time characteristics, but their $V_{DD}$ mean currents are increased a little compared with conventioanl charge pumps. The rising time upt o 15V of the proposed charge pumps is 3 times faster than that of dickson's pump at the cost of 1.5 tiems more $V_{DD}$ mean current.rrent.

• 전자공학회논문지A
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• 제33A권3호
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• pp.187-195
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• 1996

This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2$\mu$ double metal CMOS parameters. The results shwo that the CLA designed by EZMODL circuit has achived 32-bit additin time of less than 4.8NS with VDD=5.0V and 8% of transistors cn be redcued, compared to the CLA designed by MODL. The EZMODL logic style can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• 조명전기설비학회논문지
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• 제26권10호
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• pp.44-51
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• 2012

The purpose of this study is development of the diagnosis system to preventative maintenance in the on-board measuring systems for in-cab electric inspection systems of high speed railway. The on-board measuring systems can inspect precisely whether ground signal system operate stably. In this paper, we recognize characteristics of the track circuits and confirm whether the wave of current matches the on-board measuring data through the electric modeling method for high speed railway. it is necessary to develop GUI visual programs that can simulate abnormalities of the on-board measuring data in many ways, and the visual program is designed to diagnosis in the case of track circuit equipment's function decreased in advance.

• 융합신호처리학회논문지
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• 제9권3호
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• pp.224-229
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• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.36-42
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• 2009

본 논문은 modified Booth 곱셈기를 위한 고성능 파이프라인 구조를 제안하고 있다. 제안하는 곱셈기 회로는 곱셈 속도를 향상시키기 위해 가장 널리 사용되는 기술인 modified Booth 알고리즘과 파이프라인 구조에 기반을 두고 있다. 최적의 파이프라인 곱셈기를 구현하기 위해 많은 실험이 수행되었다. 파이프라인의 단 수가 증가할수록 회로 속도 향상율이 회로 크기 증가율보다 더 크며, 파이프라인 레지스터를 적절한 위치에 삽입하는 것이 중요하다는 사실이 실험 결과를 통해 확인되었다. 제안하는 modified Booth 곱셈기 회로를 Verilog HDL로 설계하였으며 0.13um 표준 셀 라이브러리를 이용하여 게이트 수준 회로로 합성하였다. 합성된 회로는 다른 곱셈기들에 비해 좋은 성능을 나타내었으며, GHz 범위에서 동작할 수 있으므로 광통신 시스템과 같은 극히 높은 성능을 필요로 하는 응용 시스템에서 사용될 수 있다.