• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.80-87
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• 2018

In recent years, due to the spread of various renewable energy power sources and the pursuit of high efficiency and low-power consumption, not only trends in the electric power industry but also the consumption, control methods, and characteristics are diversified. However, in this diversified electric power industry, the fuse (which is the core part responsible for safety) has not developed significantly in classical operation mode, and thus, fires continue to occur. In this paper, the effects of low melting-point metal plating and high melting-point metal plating on operating characteristics and IT curve movement of the fuse are investigated in a cartridge fuse, which is a classic fuse manufacturing method. The effects of plating on the thickness of the fuse are investigated, and various operating characteristics of the fuse are implemented. In addition, it is suggested that the plating of the low melting-point metal moves the rated current line of the fuse to a low rating, and moves operating characteristics to characteristics of delay operation. It is possible to design various operating characteristics using this characteristic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.360-369
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• 2008

The solar cells should be operated at the maximum power point because its output characteristics were greatly fluctuated on the variation of insolation, temperature and load. It is necessary to install an inverter among electric power converts by means of the output power of solar cell is DC. The inverter is operated supply a sinusoidal current and voltage to the load and the interactive utility line. In this paper, the proposes a photovoltaic system is designed with a step up chopper and single phase PWM voltage source inverter. Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper is operated in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature for solar cell has typical dropping character. The single phase PWM voltage source inverter is consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be develop continuously by connecting with the source of electric power for ordinary using. It can be cause the efect of saving electric power, from 10 to 20%. The single phase PWM voltage source inverter operates in situation, that its output voltage is in same phase with the utility voltage. The inverter are supplies an ac power with high factor and low level of harmonics to the load and the utility power system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of IKEEE
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• v.17 no.3
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• pp.378-384
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• 2013

We have investigated the electrical characteristics of SCR(Silicon Controlled Rectifier)-based ESD power clamp circuit with high holding voltage and dual-directional ESD protection cells for a whole-chip ESD protection. The measurement results indicate that the dimension of n/p-well and p-drift has a great effect on holding voltage (2V-5V). Also A dual-directional ESD protection circuit is designed for I/O ESD protection application. The trigger voltage and the holding voltage are measured to 5V and 3V respectively. In comparison with typical ESD protection schemes for whole-chip ESD protection, this ESD protection device can provide an effective protection for ICs against ESD pulses in the two opposite directions, so this design scheme for whole-chip ESD protection can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. Finally, a whole-chip ESD protection can be applied to 2.5~3.3V VDD applications. The robustness of the novel ESD protection cells are measured to HBM 8kV and MM 400V.

• Journal of Software Assessment and Valuation
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• v.16 no.1
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• pp.55-63
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• 2020

Lasers for optical broadband communication systems should have excellent frequency selectivity and modal stability. DFB lasers have low lasing frequency shift during high speed current modulation. In this paper, when a refractive index grating and a gain grating are simultaneously present in a DFB laser having a wavelength of 1.55 ㎛, the dielectric film is coated so that reflection does not occur on the right mirror surface, so that ρ_r=0. For the first mode, which requires a minimum gain at the threshold, the beam distribution of the oscillation mode in the longitudinal direction and the radiated power ratio P_l/P_r were analyzed and compared for the cases of the phase of ρ_l=π and π/2. If the phase of ρ_l=π, in order to obtain a low threshold current and high frequency stability, κL should be greater than 8. In the case of the phase of ρ_l=π/2, for low threshold current, κL is necessary to be 1.0, where the oscillation frequency coincides with the lattice frequency. DFB lasers with an anti-reflection coated mirror have excellent mode selectivity than 1.55um DFB lasers with two mirror facets

• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.394-399
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• 2007

In this paper, we study on a novel Buck-Boost converter of high efficiency by soft switching method. The proposed Buck-Boost converter is applied to new soft switching method in restraint of increment of switching power loss in the conventional Buck-Boost converter. The soft switching circuit is designed to modification of a energy storage inductor and a snubber circuit used by the conventional converter, and then the proposed converter is simplified. The controlling switches of the proposed converter is operated with soft switching by a partial resonance behavior. The output voltage of the converter is regulated by PWM control technique. The discontinuous mode action of current flowing into inductor makes to simplify control method and control components. The proposed Buck-Boost converter is compared with the conventional converter. Some computer simulative results and experimental results are confirmed to the validity of the analytical results.

• Journal of radiological science and technology
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• v.38 no.4
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• pp.443-449
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• 2015

An ultrasound probe has a big impact on Doppler images even though it has very high risk of frequent function-breakdowns occurring in medical ultrasound scanners. This study experimentally analyses the impacts of an ultrasonic probe's defected elements on power & color Doppler images. The results show that, the bigger the size of defected probe elements is, and the closer a group of action elements is to the center, the more the brightness of images and the velocity of Doppler diminish. When elements' defects increase in color & power Doppler images, false images are formed to be mistaken for blood-vessel plaque in neighboring regions. Accordingly, whenever element defects are suspected, we need check-up process in B-mode. From this respective, it is advisable to have primary interest in a probe and carry out continuous probe QA for ultrasonography.