• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.6-14
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• 2011

This paper presents a high-speed QR decomposition architecture for the multi-input-multi-output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 ${\mu}M$ CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 ${\times}$ 4 matrix decomposition.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.9-18
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• 2010

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.763-767
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• 2008

In this paper, to make a high performance and low power CORDIC architecture for 3D operations in mobile devices, we suggest two off-line vectoring algorithms named Angle Based Search (ABS) and Scaling Considered Search (SCS). The ABS algorithm represents a 3D vector with two angles and those angles are used as a condition for searching CORDIC rotation sequences. The SCS algorithm determines the best CORDIC rotation sequence in advance to eliminate extra scaling computation. Using the proposed algorithms, we can observe 50% of latency is reduced. Furthermore, we perform a simple analysis and discuss possible reduction of power consumption by applying voltage scaling method together with the proposed algorithm.

• The Journal of the Korea Contents Association
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• v.6 no.2
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• pp.162-168
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• 2006

This paper presents a high performance CORDIC circuit based on redundant numbers yielding a minimal number of iteration stages. The minimal number of iteration stages reflects the iteration number yielding a smaller computation error than the truncation error. The minimal number of iterations is found n-4 for $n\geq16$, where n is the number of input angle bits. The CORDIC circuit is based on a redundant number system with a constant scale factor The circuit performs sine and cosine calculations with a delay of {5 (n-4)+ 2[$log_{2}n$]}$\DeltaT$.

• Journal of IKEEE
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• v.20 no.4
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• pp.344-350
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• 2016

In this Paper, we propose an optimized method of hardware design based on Field Programmable Gate Array (FPGA) to detect rotated angle of high definition image about Extreme Contour Point (ECP) algorithm with moving video image could be not happened to translation motion, but also physical rotation motion. It was evaluated by XC7Z020 xc7z020-3clg400 FPGA board by using xilinx 14.2 tool. The much well-known method, the Coordinate Rotation Digital Integrated Computation (CORDIC) is an algorithm to estimate rotated angle between point and point. Through the result both ECP and CORDIC, our proposed design are confirmed to have similar operating speed of about 4ns with CORDIC. However, it is verified to have high performance result in terms of the hardware cost, is much better than CORDIC with cost reduction of registers and Look Up Tables (LUTs) of 108% and 91%, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.347-348
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• 2008

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.589-592
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• 2004

The CORDIC algorithm can be implemented very simple H/W, but needs a lot of latency to compute trigonometric function. The RA(Redundant Arithmetic) resolves this problem, but also has difficulty to determine the directions of micro-rotations. The pre-computed direction of micro-rotation algorithm relieves the RA of this matter. In this paper, we proposed the modified the pre-computed algorithm adopted with a table-lookup. Instead of reducing H/W complexity, its performance and calculation errors are improved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.800-807
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• 2016

We propose a fast algorithm using Extreme Contour Point (ECP) to detect the angle of rotated images, is implemented by rotation feature of one covered frame image that can be applied to correct the rotated images like in image processing for real time applications, while CORDIC is inefficient to calculate various points like high definition image since it is only possible to detect rotated angle between one point and the other point. The two advantages of this algorithm, namely compatibility to images in preprocessing by using Sobel edge process for pattern recognition. While the other one is its simplicity for rotated angle detection with cyclic shift of two $1{\times}n$ matrix set without complexity in calculation compared with CORDIC algorithm. In ECP, the edge features of the sample image of gray scale were determined using the Sobel Edge Process. Then, it was subjected to binary code conversion of 0 or 1 with circular boundary to constitute the rotation in invariant conditions. The results were extracted to extreme points of the binary image. Its components expressed not just only the features of angle ${\theta}$ but also the square of radius $r^2$ from the origin of the image. The detected angle of this algorithm is limited only to an angle below 10 degrees but it is appropriate for real time application because it can process a 200 degree with an assumption 20 frames per second. ECP algorithm has an O ($n^2$) in Big O notation that improves the execution time about 7 times the performance if CORDIC algorithm is used.