• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.620-621
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• 2008

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.264-264
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• 2016

최근에 charge trap flash (CTF) 기술은 절연막에 전하를 트랩과 디트랩 시킬 때 인접한 셀 간의 간섭현상을 최소화하여 오동작을 줄일 수 있으며 낸드 플래시 메모리 소자에 적용되고 있다. 낸드 플래시 메모리는 고집적화, 대용량화와 비휘발성 등의 장점으로 인해 핸드폰, USB, MP3와 컴퓨터 등에 이용되고 있다. 기존의 실리콘 기반의 플래시 메모리 소자는 좁은 밴드갭으로 인해 투명하지 않고 고온에서의 공정이 요구되는 문제점이 있다. 따라서, 이러한 문제점을 개선하기 위해 실리콘의 대체 물질로 산화물 반도체 기반의 플래시 메모리 소자들이 연구되고 있다. 산화물 반도체 기반의 플래시 메모리 소자는 넓은 밴드갭으로 인한 투명성을 가지고 있으며 저온에서 공정이 가능하여 투명하고 유연한 기판에 적용이 가능하다. 다양한 산화물 반도체 중에서 비정질 In-Ga-Zn-O (a-IGZO)는 비정질임에도 불구하고 우수한 전기적인 특성과 화학적 안정성을 갖기 때문에 많은 관심을 받고 있다. 플래시 메모리의 고집적화가 요구되면서 절연막에 high-k 물질을 atomic layer deposition (ALD) 방법으로 적용하고 있다. ALD 방법을 이용하면 우수한 계면 흡착력과 균일도를 가지는 박막을 정확한 두께로 형성할 수 있는 장점이 있다. 또한, high-k 물질을 절연막에 적용하면 높은 유전율로 인해 equivalent oxide thickness (EOT)를 줄일 수 있다. 특히, HfOx와 AlOx가 각각 trap layer와 blocking layer로 적용되면 program/erase 동작 속도를 증가시킬 수 있으며 넓은 밴드갭으로 인해 전하손실을 크게 줄일 수 있다. 따라서 본 연구에서는 ALD 방법으로 AlOx와 HfOx를 게이트 절연막으로 적용한 a-IGZO 기반의 thin-film transistor (TFT) 플래시 메모리 소자를 제작하여 메모리 특성을 평가하였다. 제작 방법으로는, p-Si 기판 위에 열성장을 통한 100 nm 두께의 SiO2를 형성한 뒤, 채널 형성을 위해 RF sputter를 이용하여 70 nm 두께의 a-IGZO를 증착하였다. 이후에 소스와 드레인 전극에는 150 nm 두께의 In-Sn-O (ITO)를 RF sputter를 이용하여 증착하였고, ALD 방법을 이용하여 tunnel layer에 AlOx 5 nm, trap layer에 HfOx 20 nm, blocking layer에 AlOx 30 nm를 증착하였다. 최종적으로, 상부 게이트 전극을 형성하기 위해 electron beam evaporator를 이용하여 platinum (Pt) 150 nm를 증착하였고, 계면 결함을 최소화하기 위해 퍼니스에서 질소 가스 분위기, $400^{\circ}C$, 30 분의 조건으로 열처리를 했다. 측정 결과, 103 번의 program/erase를 반복한 endurance와 104 초 동안의 retention 측정으로부터 큰 열화 없이 메모리 특성이 유지되는 것을 확인하였다. 결과적으로, high-k 물질과 산화물 반도체는 고성능과 고집적화가 요구되는 향후 플래시 메모리의 핵심적인 물질이 될 것으로 기대된다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1105-1111
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• 2006

In this paper, using low-temperature co-fired ceramic(LTCC) based system-in-package(SiP) technology, a very compact power amplifier LTCC module was designed, fabricated, and then characterized for 60 GHz wireless transmitter applications. In order to reduce the interconnection loss between a LTCC board and power amplifier monolithic microwave integrated circuits(MMIC), bond-wire transitions were optimized and high-isolated module structure was proposed to integrate the power amplifier MMIC into LTCC board. In the case of wire-bonding transition, a matching circuit was designed on the LTCC substrate and interconnection space between wires was optimized in terms of their angle. In addition, the wire-bonding structure of coplanar waveguide type was used to reduce radiation of EM-fields due to interconnection discontinuity. For high-isolated module structure, DC bias lines were fully embedded into the LTCC substrate and shielded with vias. Using 5-layer LTCC dielectrics, the power amplifier LTCC module was fabricated and its size is $4.6{\times}4.9{\times}0.5mm^3$. The fabricated module shows the gain of 10 dB and the output power of 11 dBm at P1dB compression point from 60 to 65 GHz.

• Journal of the Korean Ceramic Society
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• v.39 no.9
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• pp.822-828
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• 2002

Fabrication and electrical characterization of R. F. High-power unit capacitors were investigated to study on condition of fabrication processing for R. F. High-power unit capacitor and electrical characteristics according to addition of $ZrO_2$. The unit capacitors were fabricated using tape casting. The optimum mixture ratio of dielectrics and mixing binder for the slurry fabrication was 57.5∼60.0: 42.5∼40.0 wt%. The slurry viscosity was 4000∼5000 cps and casting state of green tape fabricated using these slurry was excellent. Optimum stacking was made by 200 kg/$cm^2$ pressure with 80$^{\circ}C$ heating. $ZrO_2$ was added to improve the electrical characteristics of unit capacitor, especially breakdown characteristics. The dielectric constant and loss factor of the unit condenser having different $ZrO_2$ amounts was not changed in the addition range of 1 to 5 wt%. Also, dielectric constant was not changed in the frequency range of 10 to 500 kHz. It was found that characteristics of resistance voltage was improved through the formation of $CaZrO_3$ and the reduction of particle size as about 3wt% $ZrO_2$ was added.

• Journal of the Korean Ceramic Society
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• v.56 no.6
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• pp.526-533
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• 2019

Indialite/cordierite glass-ceramics demonstrate excellent microwave dielectric properties such as a low dielectric constant of 4.7 and an extremely high quality factor Qf of more than 200 × 10³ GHz when crystallized at 1300℃/20 h, which are essential criteria for application to 5G/6G mobile communication systems. The glass-ceramics applied to dielectric resonators, low-temperature co-fired ceramic (LTCC) substrates, and direct casting glass substrates are reviewed in this paper. The glass-ceramics are fabricated by the crystallization of glass with cordierite composition melted at 1550℃. The dielectric resonators are composed of crystallized glass pellets made from glass rods cast in a graphite mold. The LTCC substrates are made from indialite glass-ceramic powder crystallized at a low temperature of 1000℃/1 h, and the direct casting glass-ceramic substrates are composed of crystallized glass plates cast on a graphite plate. All these materials exhibit excellent microwave dielectric properties.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.48.2-48.2
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• 2010

The effect of additives as rare-earth in dielectric materials has been studied to meet the development trend in electronics on the miniaturization with increasing the capacitance of MLCCs (multi-layered ceramic capacitors). It was reported that the addition of rare-earth oxides in dielectrics would contribute to enhance dielectric properties and high temperature stability. Especially, dysprosium and thulium are well known to the representative elements functioned as selective substitution in barium titanate with perovskite structure. The effects of these additives on microstructure and electric properties were studied. The 0.8 mol% Dy doped $BaTiO_3$ and the 1.0 mol% Tm doped $BaTiO_3$ had the highest electric properties as optimized composition, respectively. According to the increase of rare-earth contents, the growth of abnormal grains was suppressed and pyrochlore phase was formed in more than solubility limits. Furthermore, the effect of two rare-earth elements co-doped $BaTiO_3$ on the dielectric properties and insulation resistance was investigated with different concentration. The dielectric specimens with $BaTiO_3-Dy_2O_3-Tm2O_3$ system were prepared by design of experiment for improving the electric properties and sintered at $1320^{\circ}C$ for 2h in a reducing atmosphere. The dielectric properties were evaluated from -55 to $125^{\circ}C$ (at $1KHz{\pm}10%$ and $1.0{\pm}0.2V$) and the insulation resistance was examined at 16V for 2 min. The morphology and crystallinity of the specimens were determined by microstructural and phase analysis.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.37-43
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• 2009

Silicon dioxide as gate dielectrics was grown at $400^{\circ}C$ on a polycrystalline Si substrate by inductively coupled plasma oxidation using a mixture of $O_2$ and $N_2O$ to improve the performance of polycrystalline Si thin film transistors. In conventional high-temperature $N_2O$ annealing, nitrogen can be supplied to the $Si/SiO_2$ interface because a NO molecule can diffuse through the oxide. However, it was found that nitrogen cannot be supplied to the Si/$SiO_2$ interface by plasma oxidation as the $N_2O$ molecule is broken in the plasma and because a dense Si-N bond is formed at the $SiO_2$ surface, preventing further diffusion of nitrogen into the oxide. Nitrogen was added to the $Si/SiO_2$ interface by the plasma oxidation of mixtures of $O_2/N_2O$ gas, leading to an enhancement of the field effect mobility of polycrystalline Si TFTs due to the reduction in the number of trap densities at the interface and at the Si grain boundaries due to nitrogen passivation.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.304.1-304.1
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• 2014

Flat-panel displays have been growing as an essential everyday product in the current information/communication ages in the unprecedented speed. The forward-coming applications require light-weightness, higher speed, higher resolution, and lower power consumption, along with the relevant cost. Such specifications demand for a new concept-based materials and applications, unlike Si-based technologies, such as amorphous Si and polycrystalline Si thin film transistors. Since the introduction of the first concept on the oxide-based thin film transistors by Hosono et al., amorphous oxide thin film transistors have been gaining academic/industrial interest, owing to the facile synthesis and reproducible processing despite of a couple of shortcomings. The current work places its main emphasis on the binary oxides composed of ZnO and SnO2. RF sputtering was applied to the fabrication of amorphous oxide thin film devices, in the form of bottom-gated structures involving highly-doped Si wafers as gate materials and thermal oxide (SiO2) as gate dielectrics. The physical/chemical features were characterized using atomic force microscopy for surface morphology, spectroscopic ellipsometry for optical parameters, X-ray diffraction for crystallinity, and X-ray photoelectron spectroscopy for identification of chemical states. The combined characterizations on Zn-Sn-O thin films are discussed in comparison with the device performance based on thin film transistors involving Zn-Sn-O thin films as channel materials, with the aim to optimizing high-performance thin film transistors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.191-191
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• 2007

유효 산화막 두께가 약 2.0nm 정도의 $ZrO_2$ 절연막 위에 Ta-Mo 금속 합금과 Ru-Zr 금속 합금을 Co-sputtering 방법을 이용하여 여러 가지 일함수를 갖는 MOS capacitor를 제작하여 전기적 재료적 특성에 관하여 연구를 하였다. 그 결과 각각의 금속 합금 게이트는 4.1eV 에서 5.1eV 사이의 다양한 일함수를 나타냈으며, $400^{\circ}C$, $500^{\circ}C$, $600^{\circ}C$, $700^{\circ}C$, $800^{\circ}C$ RTA 후의 C-V특성 곡선 및 I-V 측정을 통하여 누설전류를 확인하였다. 그 결과 Ta-Mo 금속 합금의 경우 스퍼터링 파워가 100W/70W에서 NMOS에 적합한 일함수를 가졌으며, Ru-Zr 금속 합금의 경우 스퍼터링 파워가 50W/100W에서 NMOS에 적합한 일함수를 가졌다. 열처리 후의 C-V특성 곡선에서도 정전용랑 값이 거의 변하지 않았으며 평탄 전압의 변화도 거의 없었다. 누설전류 특성에서는 물리적 두께가 비슷한 기존의 $SiO_2$ 절연막에서 실험결과와 비교하여 약 100배 정도 감소되었음을 알 수 있었다. 또한 기존의 실험들에서 나타난 열처리 후의 $ZrO_2$ 절연막과 Si 기판 사이의 Interfacial layer 의 동반 두께 증가로 인한 전기적 특성 저하가 나타나지 않는 줄은 특성을 보여준다.