• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.459-466
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• 1999

I broadband ISDN every packet will show different result if it would be processed according to its usage by the server. That is, normal data won't show big differences if they would be processed at normal speed. But it will improve the quality of service to process some kinds of data - for example real time video or voice type data or some data for a bid to by something through the internet - more fast than the normal type data. solution for this problem was suggested - priority packets. But the analyses of them are under way. Son in this paper a switching system for an output queuing model in a single server was assumed and some packets were given priorities and analysed. And correlation, simulating real life situation, was given too. These packets were analysed through three cases, first packets having no correlation, second packets having only correlation and finally packets having priority three cases, first packets having no correlation, second packets having only correlation and finally packets having priority and correlation. The result showed that correlation doesn't affect the mean delay time and the high priority packets have improved mean delay time regardless of the arrival rate. Those packets were assumed to be fixed-sized like ATM fixed-sized cell and the contention strategy was assumed to be short bus contention method for the output queue, and the mean delay length and the maximum 버퍼 length not to lose any packets were analysed.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.15-22
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• 2019

In these days, importance of the power electronic devices and modules keeps increasing due to electric vehicles and energy saving requirements. However, current silicon-based power devices showed several limitations. Therefore, wide band gap (WBG) semiconductors such as SiC, GaN, and $Ga_2O_3$ have been developed to replace the silicon power devices. WBG devices show superior performances in terms of device operation in harsh environments such as higher temperatures, voltages and switching speed than silicon-based technology. In power devices, the reliability of the devices and module package is the critically important to guarantee the normal operation and lifetime of the devices. In this paper, we reviewed the recent trends of the power devices based on WBG semiconductors as well as expected future technology. We also presented an overview of the recent package module and fabrication technologies such as direct bonded copper and active metal brazing technology. In addition, the recent heat management technologies of the power modules, which should be improved due to the increased power density in high temperature environments, are described.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1096-1101
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• 2004

By a tremendous expansion of Internet users, there's a number effects that cause the phenomenon of bottlenecked switching packets from routers. In order to tear down this problem, distributed system is applicable to almost every highly performed router systems. The main processor of distributed system, which manages routing table, commands IPC to delivering the forwarding table line processor that eases functionalities of the router. This makes the system having wired-speed forwarding function based on the hardware so that the performance of the network can be enhanced. Therefore, IPC, which assign a part of router, is necessary to exchange data smoothly and the constitution of IPC using Ethernet is widely adapted as a method for saving investment. In this paper, R-IPC mechanism improve the packet-processing rate over 10% through changed from defect of conventional Ethernet IPC, that is, 2 layer processing to TCP/IP or UDP/ IP into 1 layer processing for efficient packet forwarding.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.4
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• pp.328-339
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• 2006

In this paper the characteristic analysis of a single-phase switched reluctance motor (SRM) drive system with power factor correction (PFC) circuit is presented. The SRM is a low cost, simple and has a good high speed performance. The SRM drive with diode rectifier and filter capacitor has a low power factor because of short switch on time of capacitor. A novel switching topologic is presented to improve power factor and reduce torque ripple based on analysis of PFC circuit. Accordingly the SRM drive system with PFC circuit is also presented. Through the numerical analysis of the system, the toque ripple, power factor and efficiency with the change of rotary speed, load torque and capacity of the capacitor are achieved and compared with actual measured value.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.843-846
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• 2004

For the fast growing Liquid Crystal Display (LCD) TV market, it is essential to make the LCD panels to show moving images without any visual difficulties such as blurring or tailing. Owing to reduction of the cell gap and the improved Liquid Crystal (LC) mixtures with low viscosity, it is possible that our S-IPS TFT-LCDs feature a response time (R/T) as fast as 1-frame time (16ms) for a white-black operation and less than a 16rns in all gray levels without Over Driving Circuit (ODC) technology. Currently, mass production of the large size IPS panels with high speed has been successfully achieved. In order to achieve faster response time, new LC mixtures have been developed, optimizing the physical properties of rotational viscosity (${\gamma}$1) and elastic constants (Kii). Also, the LC mixtures with high elastic constant allow us to increase the cell gap. In this paper, realization of fast switching time in IPS mode with optimized '${\gamma}$1/Kii' parameter in the LC mixtures forms the core of this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.