• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.616-618
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• 1996

This paper presents an unipolar PWM which commutated switching device only in a half period. This method reduced switching loss significantly because of decreasing switching number in n period. In high speed motor drive needed high frequency above 300 Hz fundamental frequency, this method is suited very well. This paper described the principle of unipolar PWM method, analyzed harmonic spectrum and compared with bipolar PWM, Modified PWM and Overmodulation method in switching loss.

• 전기학회논문지P
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• 제51권1호
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• pp.10-17
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• 2002

Due to the development of information communication field, the interest of the SMPS(Switched Mode Power Supply) is increased. The size and weight of SMPS are decided by inductor, capacitor and transformer. Thus, the low loss converter which is operated in high speed switching is required. The resonant FB DC-DC converter is able to operate in high speed switching and apply to high power field because the switching loss is low. In this thesis, it is proposed to control strategy for constant output power of resonant FB DC-DC converter in variable input voltage. The proposed control system is a digital I-PD type control and apply to phase-shift resonant type controller. The output voltage tracks reference without steady state error in variable input voltage. The validity of proposed control strategy is verified from results of simulation and experiment.

• Journal of Power Electronics
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• 제9권2호
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• pp.308-319
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• 2009

An increasing number of power electronic applications require high power density. Therefore, the switching frequency and switching speed have to be raised considerably. However, the very fast switching transients induce a strong voltage and current ringing. In this work, a novel damping concept is introduced where the parasitic wiring inductances are advantageously magnetically coupled with a damping layer for attenuating these unwanted oscillations. The proposed damping layer can be implemented using standard materials and printed circuit board manufacturing processes. The system behavior is analyzed in detail and design guidelines for a damping layer with optimized RC termination network are given. The effectiveness of the introduced layer is determined by layout parasitics which are calculated by application of the Partial Element Equivalent Circuit (PEEC) simulation method. Finally, simulations and measurements on a laboratory prototype demonstrate the good performance of the proposed damping approach.

• 한국철도학회논문집
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• 제15권3호
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• pp.244-250
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• 2012

본 논문에서는 차세대 고속철도 구동 인버터 시스템의 고조파로 인한 전자기적 소음을 줄이기 위해 RCF-PWM(Random Carrier Frequency Pulse Width Modulation)을 적용한 인버터 구동시스템을 개발하였다. RCF-PWM 방식은 인버터 스위칭 주파수를 전력용 반도체의 최대 스위칭 주파수와 최소 스위칭 주파수 사이에서 임의적으로 변화시키며 PWM을 수행하는 방법이다. 본 연구의 타당성을 확인하기위해서 RCF-PWM이 적용된 차세대 고속전철 시스템을 설계하여 MATLAB/Simulink 기반의 시뮬레이터를 개발하고 이를 이용하여 일정한 스위칭 주파수를 사용하는 정규적인 SVPWM 방식과 RCF-PWM 방식의 시험결과를 비교 분석하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 학술대회 논문집 전문대학교육위원
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• pp.127-133
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• 2001

In SRM drive, the ON OFF angles of each phase switch should be accurately controlled in order to control the torque and speed stably. The accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to control the SRM power circuit, respectively. However, as the speed increases, the amount of the switching angle deviation from the preset values is also increased. Therefore, the low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper. As a result, a stable high speed SRM drive can be achieved by the high resolution switching angle control and it is verified from the experiments that the proposed encoder and logic controller can be a powerful candidate for the practical low cost SRM drive.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Journal of Power Electronics
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• 제11권4호
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• pp.520-526
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• 2011

This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2009년도 춘계학술대회 논문집
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• pp.384-387
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• 2009

There is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. Many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation (PWM) converter. Especially, the phase shift full bridge zero voltage switching PWM techniques are thought must desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.