• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1227-1232
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• 2008

High-speed train of push-pull type called as G7 train has been developed and chosen as the model of KTX-II which will be operated on Honam Line nexr year. However, the EMU-type high-speed train appeared to be the recent trend that foreign markets have shown. Also, in the near future, a great number of new train sets are needed to accommodate the increased passengers in our country. Thus, development of the high-speed EMU was decided, planned, and started. In the development, included were almost all fundamental key technologies such as noise and vibration reduction in a passenger cabin, running characteristics, aerodynamic analysis, crashworthiness evaluation, EMI/EMC analysis, design of the cooling system for the propulsion control system, enhanced performance of transformer and switching converters, synchronous traction motor with permanent magnets, new design of front nose and ergonomic interiors, application of advanced information technology(IT) and smart sensors and the cost reduction of construction of railway bridges, etc. Each key technologies are carried out as sub-project independently but under the supervision of a project. The project will develop the high advanced level of technologies and provide necessary know-why's and support the team in charge of the development of the high-speed EMU, Hyundai Rotem Co. Ltd. The high-speed EMU will be successfully developed with the support of the project.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.231-233
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• 1991

This paper discribes a study on the switching character of MOS-GTO and the design of gate drive circuit. Chopping power supply converter, synchronious and asyncronious motor speed adjustment, inverter, etc., needs low drive energy "high frequency" switches. To fulfill these need, switches must have rapid switching time and insulated gate control. MOS-GTO structure is well suited to these constraints. The power switch is serial installation of a GTO thyrister and a MOS Transistor. The gate of the GTO is linked to positive pole of the cascode structure via a MOS high voltage transistor and ground via a transient absorber diode. This high performance MOS-GTO assembly considerably increases the strength which facilitate the drive of GTO thyristers.

• Journal of IKEEE
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• v.17 no.3
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• pp.365-370
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• 2013

Power MOSFET is developed in power savings, high efficiency, small size, high reliability, fast switching, and low noise. Power MOSFET can be used in high-speed switching transistors devices. Recently attention given to the motor and the application of various technologies. Power MOSFET is a voltage-driven approach switching device and designed to handle on large power, power supplies, converters, motor controllers. In this paper, the 400 V Planar type, and the trench type for realization of low on-resistance are designed. Trench Gate Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.190-193
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• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.23-24
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• 2013

In recent years, ISG (Integrated Starter and Generator) system receives a great attention for electric electrification of normal gasoline vehicle. As a cost-effect machine design, an ISG without a permanent magnet is considered. A 12slot-10pole field-excitation flux-switching synchronous machine (FEFSSM) is designed and analyzed via JMAG. The active parts such as the field excitation coil and armature coil are located on the stator. The rotor part consisting of single piece iron makes it more robust and suitable to apply for high speed motor drive system application coupled with reduction belt. The design target is the motor with a maximum torque of 40Nm, a maximum power of 10kW and a maximum speed of 14000 rpm. In this paper, design optimization method is proposed for high torque capability.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.627-630
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• 1991

This study is about vector controlled inverter for high quality elevator drive that is to improve the settling accuracy of elevator car and passenger's comfort in commercial buildings. In this study, an instantaneous space vector control type inverter was used to reduce the torque ripple ant to improve the velocity follow-up. This method calculates Instantaneous actual output torque and flux of induction motor by voltage and current, then compares them with a reference values by a speed regulator. The outputs of comparators select a switching mode, for an optimal voltage vector. Also, this study used IGBT (Insulated Gate Bipolar-Transistor), a high speed switching element, to reduce sound noise level, and DSP (Digital Signal Processor) was used to improve the reliability of the control circuit by fully digitalization.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.493-496
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• 1997

This paper constructed the experimental system which is able to drive in series or separately excited by switching of the field winding, using a DC motor and obtained the characteristics of efficiency with speed and torque of each motor's type through the experiment. From this result controlled drive which is able to series DCM or separately excited DCM in the optimal point of efficiency as finding the types of motor having maximum efficiency with torque and speed. By performing high efficiency tracking drive, it is expected that energy consumption of power source with limited energy density would be reduced, and so utility efficiency would be improved.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1847-1850
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• 2002

In this paper, MPLS Router module supporting Differentiated Service(Diffserv) for quality of Service (QoS) and High-speed switching is proposed and implemented. And we compare and analyze the proposed architecture with the conventional one in terms of CLR (Cell Loss Rate) and average delay. Switch is an extended system of Queue of each VOQ and PHB in the manner of Input Queuing for QoS. Algorithm, Priority-iSLIP is used for its scheduling algorithm. The proposed architecture is modeled in C++ and verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2620-2633
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• 1996

In this paper, a new high-speed local area network using a dual mode switching access (DMSA) protocol implemented on a dual unidirectional bus is described. By utilizing the implicit positionalordering of stations on a unidirectional bus, the proposed system switches between random access mode and the token access model withoug unnecessary delay. Therefore, unlike other hybrid systems such as Buzz-net and Z-net, DMSA does not show a rapid degradation in performance as the load increases. We obtain the average channel utilization and the average access delay by using a simplified analytic model. The numerical results obtained via analysis are compared to the simulation resuls for a partial validation of the approximate model. The performance characteristics of DMSA are superior delay-throughput characteristics at light and medium loads, compared to compared to other LAN systems, and the capability of providing a single active station with full capabity of the channel.