• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.1
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• pp.54-61
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• 2000

Conventionally, ZVS FB DC/DC converter was controlled by monolithic IC UC3879, which includes the functions of oscillator, error amplifier and phase-shift circuit. Also, microprocessor and DSP have been widely used for the remote control and for the immediate waveform control in ZVS FB DC/DC converter. However the conventional microprocessor controller is complex and difficult to control because the controller consists of analog and digital parts. In the case of the control of FB DC/DC converter, the output is required of driving a direct signal to the switch drive circuits by the digital controller. So, this paper presents the method and realization of designing the digital-to-phase shift PWM circuit controlled by DSP (TMX320C32) in a 2,500A, 40㎾ ZVS FB DC/DC converter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.830-833
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• 2004

Voltage step-down characteristics of Ring/Dot type piezoelectric transformer were examined with increasing input voltage from $10\;V_{pp}$ to $140V_{pp}$. Then the output load resistance was fixed to $125\;\Omega$. The voltage gain showed constant value till the input voltage of $70\;V_{pp}$. And then it linearly decreased till the input voltage of $140V_{pp}$. The output voltage of fabricated piezoelectric transformer increased with increasing input voltage. And driving frequencies when the output voltage was maximum value were changed according to input voltage. Frequency shifts and temperature rise of fabricated sample showed 2 kHz, $13^{\circ}C$, respectively when input voltage was changed from $10\;V_{pp}$ to $140V_{pp}$. Because of the temperature rise of fabricated piezoelectric transformer, the step-down characteristics of it was deteriorated above the input voltage of $70\;V_{pp}$.

• Journal of Magnetics
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• v.12 no.1
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• pp.35-39
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• 2007

A highly sensitive magnetic sensor using the Giant MagnetoImpedance effect has been developed. The sensor performance is studied and estimated. The sensor circuitry consists of a square wave generator (driving source), a sensing element in a form of composite wire of a 25 $\mu$m copper core electrodeposited with a thin layer of soft magnetic material ($Ni_{80}Fe_{20}$), and two amplifier stages for improving the gain, switching mechanism, scaler circuit, an AC power source driving the permeability of the magnetic coating layer of the sensing element into a dynamic state, and a signal pickup LC circuit formed by a pickup coil and an capacitor. Experimental studies on sensor have been carried out to investigate the key parameters in relation to the sensor sensitivity and resolution. The results showed that for high sensitivity and resolution, the frequency and magnitude of the ac driving current through the sensing element each has an optimum value, the resonance frequency of the signal pickup LC circuit should be equal to or twice as the driving frequency on the sensing element, and the anisotropy of the magnetic coating layer of the sensing wire element should be longitudinal.

• Korean Journal of Optics and Photonics
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• v.17 no.5
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• pp.396-400
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• 2006

We present a weather-insensitive optical free-space communication method supporting optical packet channels. It operates optical fiber amplifiers in gain-saturation regions. When the propagation loss gets too high, it decreases the average packet rate, or the average packet length, or both, to increase the optical power level launched into the free-space. As a demonstration, we transmit $8{\times}10$ Gigabit Ethernet channels over a terrestrial distance of 2.4 km. One gain-saturated free-space optical repeater is used at the halfway point.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.28-30
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• 2018

본 논문에서는 전이중 통신 방식을 사용하는 DOCSIS 3.1 시스템의 자기간섭 제거를 위한 자기간섭신호의 채널 및 비선형 왜곡 요소를 추정하는 기술을 제안한다. DOCSIS 3.1 시스템의 전이중 통신 방식은 일반적으로 가입자 단말인 CM (Cable Modem) 과 케이블방송신호 송신 시스템인 CMTS (Cable Modem Termination System) 사이의 상하향 통신을 시간/주파수의 분할 없이 동시에 수행하는 통신 방식이다. CMTS 에서 CM 의 신호를 수신함과 동시에 CMTS 신호를 송신하는 경우 고출력의 CMTS 송출신호가 CMTS 의 수신기로 인가되는 자기간섭 현상이 발생하게 된다. 이렇게 인가되는 자기간섭신호는 고출력 증폭기 (HPA: High - Power Amplifier) 및 Feedback 채널의 영향으로 크게 왜곡되어 수신된다. 따라서 자기간섭신호를 제거하고 CM 의 신호를 원활하게 복조하기 위해서는 자기간섭신호의 왜곡 요소룰 추정 및 보상하는 절차가 반드시 필요하다. 본 논문에서는 자기간섭신호의 HPA 에서 발생하는 비선형 왜곡 요소 및 Feedback 채널의 영향으로 발생하는 채널 요소를 추정하는 기술을 제안하고 성능을 분석한다. 제안된 기술은 간단한 연산기반으로 왜곡요소의 추정이 가능하며 반복추정을 통해 성능을 효과적으로 향상시키는 것이 가능하다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.5
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• pp.547-555
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• 2008

This parer proposed the path mismatch detection and compensation algorithm with closed form for linear amplification with non-linear components(LINC) system implementation. The LINC system has a merit of using the high efficient amplifier by transferring the non-constant envelop signal which is high peak to average signal ratio into constant envelop signal. However, the performance degradation is very sensitive to the path mismatch such as an amplitude mismatch and a phase mismatch. In order to improve the path mismatch, the error detection and compensation method is introduced by the use of four test signals. Since the presented method has the closed form solution, the efficient and fast detection is available. The digital-IF structure of LINC system applied by the proposed error detection and compensation algorithm was implemented. The performance was evaluated with the IEEE 802.16 WiMAX baseband sinal which has 7 MHz channel bandwidth and 16-QAM. The Error Vector Magnitude(EVM) of -37.37 dB was obtained through performance test, which meets performance requirement of -24 dB EVM. As a result, the introduced error detection and compensation method was verified to improve the LINC system performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.509-514
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• 2003

Mach-Zehnder interferometric wavelength converters with monolithically integrated semiconductor optical amplifiers (SOA's) have been fabricated and characteristics of wavelength conversion at 10 Gb/s have been investigated for wavelength span of 40 nm. The devices have been achieved by using a butt-joint combination of buried ridge structure type SOA's and passive waveguides. In the integration, a new method has been applied that removes p+InP cladding layer leading to high propagation loss and forms simultaneously the current blocking and the cladding layer using undoped InP. The module packaging has been achieved by using a titled fiber array for effective coupling into the tilted waveguide in the wavelength converter. Using the module, wavelength conversion with power penalty lower than 1 ㏈ at 10 Gb/s has been demonstrated for wavelength span of 40 nm. In addition, it is show that the module can provide 2R (re-amplification, re-shaping) operation by demonstrating the conversion with the negative penalty.