• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.2
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• pp.91-97
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• 2000

Tn this paper, a novel control circuit applicable to the error sensor loop block in the feedforward linearizer system is proposed. The proposed control circuit is applied to the error sensor loop block, where in the 11dB power range, it operates stably, and makes main carrier signals to be eliminated more than 40dB below 3$\^$rd/ order IM level. In the operating point, the amplitude control error is 0.05∼0.12dB, and the phase control error is smaller than 0.02。. It is verified theoretically as well as experimentally that the control circuit can precisely compensate the variation of nonlinear characteristics in a high power amplifier, due to the variations of input power, operating temperature, humidity and the other system environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5A
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• pp.363-371
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• 2009

OFDM(orthogonal frequency division multiplexing) is very effective forhigh data rate transmission system. However, communication performance becomes worse because of nonlinear distortion resulting from the PAPR. In this paper, we like to propose a tone-controlled CI/OFDM system including the TMD (inter-modulation distortion) reduction method in order to improve the BER performance. In this tone-controlled CI/OFDM system, control tone is additionally inserted in each data symbol of CI/OFDM system to make the CI/OFDM lower the PAPR and robust to nonlinear distortion. So, tone-controlled CI/OFDM using the IMD reduction method shows better BER (bit error rate) performance than methods based on PAPR reduction.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.8
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• pp.740-747
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• 2015

Recently, mobile communication systems using the millimeter-wave frequency band have been proposed, and the importance of efficient compensation of the nonlinearity caused by 60 GHz high-power amplifiers(HPAs) is increasing. In this paper, we propose a predistorter structure based on multiple coefficient sets which are separately used to different ranges of input power values. These ranges correspond to varying levels of nonlinearity characteristics. The structure is applied to the 60 GHz HPA FMM5715X and the performance of correcting the nonlinearity of LTE signals is evaluated. Evaluation results using a hardware testbed demonstrate that the proposed predistorter structure achieves the maximum of 6 dB gain over the conventional method in terms of the adjacent channel leakage ratio(ACLR).

• Journal of IKEEE
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• v.24 no.1
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• pp.72-80
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• 2020

This paper describes the design and fabrication of a BUC(Block Up-converter) which is a component of a FST (Flyaway Satellite Terminal), one of the ET(Earth Terminal) of the military satellite. BUC is physically composed of an up-converter module, a high power amplifier module, a receive band suppression filter, a housing, and a cable assembly. It was designed using simulator AWR to satisfy the electrical characteristics of BUC's such as maximum output power, gain, unwanted signal, and intermodulation. The maximum output power and gain characteristics were measured at 43.4dBm and 51.8dB, respectively. The unwanted wave and intermodulation characteristics were -73.5dBc and -31.9dBc, respectively. Of the electrical requirements of Table 1, not only the above four but also all of the items were confirmed to be satisfied.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.7
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• pp.1044-1052
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• 1999

A 2-stage 1 watt MMIC(Monolithic Microwave Integrated Circuits) HPA(High Power Amplifiers) at 20 GHz band has been designed and fabricated. The $0.15\mu\textrm{m}$ with the width of $400\mu\textrm{m}$for single device pHEMT technology was used for the fabrication of this MMIC HPA. Due to the series feedback technique from source to ground, bias circuits and stabilization circuits on the main microstrip line, the stability factors(Ks) are more than one at full frequency. The independent operation for each stage and excellent S11, S22 less than -20 dB have been obtained by using lange couplers. For beginning the easy design, linear S-parameters have been extracted from the nonlinear equivalent circuit in foundry library, and equivalent circuits of devices at in/output ports were calculated from this S-parameters. The measured performances, which are in well agreement with the predicted ones, showed the MMIC HPA in this paper has the minimum 15 dB of linear gain, -20 dB of reflection coefficients and 31 dBm of output power over 17~25 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.744-751
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• 2004

This paper presents the implementation of the low cost and high speed RF ATE(Automatic Test Equipment) system, which can be a reasonable solution for reducing the test cost of RF devices. This paper suggests high speed and precise measurement capabilities which are realized by the 16 independent RF ports with high speed switching time and high accuracy digitizer using the industry standard Versus module eXtensions for Instrument(VXI) General Purpose Interface Bus(GPIB) interfaces. Also, the system has the capabilities of quad-site test which can dramatically increase the device throughput. This paper concludes with the demonstration of the implemented ATE system through the setup of RF Power Amplifier Module(PAM), which is under the most competitive market situation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.430-433
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• 2017

This paper presents a S/C/X-band LNA MMIC with resistive feedback structure in 0.25 um GaN HEMT process. The GaN devices have advantages as a high output power device having high breakdown voltage, energy band gap and stability at high temperature. Since the receiver using the GaN device with high linearity can be implemented without a limiter, the noise figure of the receiver can be improved and the size of receiver module can be reduced. The proposed GaN LNA MMIC based on 0.25 um GaN HEMT device is achieved the gain of > 15 dB, the noise figure of < 3 dB, the input return loss of > 13 dB, and the output return loss of > 8 dB in the S/C/X-band. The current consumption of GaN LNA MMIC is 70 mA with the drain voltage 20 V and the gate voltage -3 V.