• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2021.10a
• /
• pp.199-201
• /
• 2021

The Internet of Things (IoT) is a technology that can organically connect people and things without time and space constraints by using communication network technology and sensors, and transmit and receive data in real time. The IoT used in all industrial fields has limitations in terms of storage allocation, such as device size, memory capacity, and data transmission performance, so it is important to manage power consumption to effectively utilize the limited battery capacity. In the prior research, there is a problem in that security is deteriorated instead of improving power efficiency by lightening the security algorithm of the encryption module. In this study, we proposes a low-power security architecture that can utilize high-performance security algorithms in the IoT environment. This can provide high security and power efficiency by using relatively complex security modules in low-power environments by executing security modules only when threat detection is required based on inspection results.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.15 no.6
• /
• pp.2148-2167
• /
• 2021

The proliferation of the Internet of Things (IoT) technologies and applications, especially the rapid rise in the use of mobile devices, from individuals to organizations, has led to the fundamental role of secure wireless networks in all aspects of services that presented with many opportunities and challenges. To ensure the CIA (confidentiality, integrity and accessibility) security model of the networks security and high efficiency of performance results in various resource-constrained applications and environments of the IoT platform, DDO-(data-driven operation) based constructions have been introduced as a primitive design that meet the demand of high speed encryption systems. Among of them, the TMN-family ciphers which were proposed by Tuan P.M., Do Thi B., etc., in 2016, are entirely suitable approaches for various communication applications of wireless mobile networks (WMNs) and advanced wireless sensor networks (WSNs) with high flexibility, applicability and mobility shown in two different algorithm selections, TMN64 and TMN128. The two ciphers provide strong security against known cryptanalysis, such as linear attacks and differential attacks. In this study, we demonstrate new probability results on the security of the two TMN construction versions - TMN64 and TMN128, by proposing efficient related-key recovery attacks. The high probability characteristics (DCs) are constructed under the related-key differential properties on a full number of function rounds of TMN64 and TMN128, as 10-rounds and 12-rounds, respectively. Hence, the amplified boomerang attacks can be applied to break these two ciphers with appropriate complexity of data and time consumptions. The work is expected to be extended and improved with the latest BCT technique for better cryptanalytic results in further research.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.1
• /
• pp.27-34
• /
• 2021

In this paper, we propose a copyright protection scheme for real-time streaming of HEVC(High Efficiency Video Coding) based realistic content. Previous research uses encryption and modular operation for copyright pre-protection and copyright post-protection, which causes delays in ultra high resolution video. The proposed scheme maximizes parallelism by using thread pool based DRM(Digital Rights Management) packaging with only HEVC's CABAC(Context Adaptive Binary Arithmetic Coding) codec and GPU based high-speed bit operation(XOR), thus enabling real-time copyright protection. As a result of comparing this scheme with previous research at three resolutions, PSNR showed an average of 8 times higher performance, and the process speed showed an average of 18 times difference. In addition, as a result of comparing the robustness of the forensic mark, the filter and noise attack, which showed the largest and smallest difference, with a 27-fold difference in recompression attacks, showed an 8-fold difference.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.2
• /
• pp.11-19
• /
• 2020

Modern GPU can execute general purpose computation on the graphic processing unit, and provide high performance by exploiting many core on GPU. To run AES algorithm efficiently, parallel computational resources are required. However, computational resource of CPU architecture are not enough to cryptographic algorithm such as AES whereas GPU architecture has mass parallel computation resources. Therefore, this paper reduce the time to execute AES by employing parallel computational resource on GPGPU. Unfortunately, AES cannot utilize computational resource on GPGPU since it isn't suitable to GPGPU architecture. In this paper, IPC based dynamic SM management technique are proposed to efficiently execute AES on GPGPU. IPC based dynamic SM management can increase and decrease the number of active SMs by using IPC in run-time. According to simulation results, proposed technique improve the performance by increasing resource utilization compared to baseline GPGPU architecture. The results show that AES improve the performance by 41.2% on average.

• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.6
• /
• pp.205-212
• /
• 2015

SSH provides a secure, encrypted communication channel between two end point systems using public key encryption. But SSH brute force attack is one of the most significant attacks. This kind of attack aims to login to the SSH server by continually guessing a large number of user account and password combinations. In this paper, we analyze logs of SSH brute force attacks in 2014 and propose a failed-log based detection mechanism in high performance computing service environment.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2007.05a
• /
• pp.448-452
• /
• 2007

Many industrial operations require continuous or nearly-continuous operation of machines, which if interrupted can result in significant financial loss. The condition monitoring of these machines has received considerable attention recent years. Rapid developments in semiconductor, computing, and communication with a remote site have led to a new generation of sensor called "smart" sensors which are capable of wireless communication with a remote site. The purpose of this research is the development of smart sensor using which can on-line perform condition monitoring. This system is addressed to detect conditions that may lead to equipment failure when it is running. Moreover it will reduce condition monitoring expense using low cost MEMS accelerometer. This sensor can receive data in real-time or periodic time from MEMS accelerometer. Furthermore, this system is capable for signal preprocessing task (High Pass Filter, Low Pass Filter and Gain Amplifier) and analog to digital converter (A/D) which is controlled by CPU. A/D converter that converts 10bit digital data is used. This sensor communicates with a remote site PC using TCP/IP protocols. Wireless LAN contain IEEE 802.11i-PSK or WPA (PSK, TKIP) encryption. Developed sensor executes performance tests for data acquisition accuracy estimations.

• KIPS Transactions on Computer and Communication Systems
• /
• v.9 no.5
• /
• pp.107-112
• /
• 2020

Ultra-lightweight password CHAM is an algorithm with efficient addition, rotation and XOR operations on resource constrained devices. CHAM shows high computational performance, especially on IoT platforms. However, lightweight block encryption algorithms used on the Internet of Things may be vulnerable to side channel analysis. In this paper, we demonstrate the vulnerability to side channel attack by attempting a first power analysis attack against CHAM. In addition, a safe algorithm was proposed and implemented by applying a masking technique to safely defend the attack. This implementation implements an efficient and secure CHAM block cipher using the instruction set of an 8-bit AVR processor.

• Annual Conference of KIPS
• /
• 2003.11c
• /
• pp.2021-2024
• /
• 2003

Information security is becoming a more important factor in distribution of digital contents. Generally, illegal facsimile of high-quality multimedia products such as DVDs, MP3s and AACs is possible without damaging quality. Thus, the illegal distribution of duplicated contents on the Web is causing digital content providers great economic loss. Therefore, a study of security and efficient distribution of digital contents is required. The most important issues in the design of a digital content distribution system are user convenience, execution speed and security. In this study, we designed a digital contents distribution system that uses web caching technology and encryption/decryption techniques in hierarchical structures. We propose a digital content distribution system that improves user convenience, security and execution speed. The superior performance of the proposed system has been proven in the tests. The results of experiment show that the developed system has improved the security of DC without decreasing process speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.575-577
• /
• 2017

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.3_4
• /
• pp.149-159
• /
• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.