• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2019.06a
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• pp.144-146
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• 2019

Recently, according to the rapid development of surveillance information, closed-circuit television (CCTV) has become an indispensable component in security systems. A lot of advanced technologies of encryption and compression are implementing to improve the performance and security levels of the CCTV system. Especially, 360 video CCTV streaming is promising for surveillance without blind areas. However, compared to previous systems, 360 CCTV requires large bandwidth and low latency. Therefore, it requires more efficiently effort to improve the CCTV system performance. In order to meet the demands of 360 CCTV streaming, transcoding is an essential process to enhance the current CCTV system. Moreover, encryption algorithm is also an important priority in security system. In this paper, we propose a real-time transcoding solution in combination with the ARIA and AES algorithms. Experimental results prove that the proposed method has achieved around 195% speed up transcoding compared to FFMPEG libx265 method. Furthermore, the proposed system can handle multiple transcoding sessions simultaneously at high performance for both live 360 CCTV system and existing CCTV system.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.43-51
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• 2017

MANET consists of only wireless nodes having limited processing capability. It processes routing and data transmission through cooperation among each other. And it is exposed to many attack threats due to the dynamic topology by movement of nodes and multi-hop communication. Therefore, the reliability of transmitted data between nodes must be improved and security of integrity must be high. In this paper, we propose a method to increase the reliability of transmitted data by providing a secure cryptography protocol. The proposed method used a hierarchical structure to provide smooth cryptographic services. The cluster authentication node issues the cluster authentication key pair and unique key to the nodes. The nodes performs the encryption through two steps of encryption using cluster public key and block encryption using unique key. Because of this, the robustness against data forgery attacks was heightened. The superior performance of the proposed method can be confirmed through comparative experiment with the existing security routing method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.201-204
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• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Journal of IKEEE
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• v.18 no.3
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• pp.328-334
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• 2014

This paper proposes an optical encryption and decryption system for OFB(Output Feedback Block) encryption algorithm. The proposed scheme uses a dual-encoding technique in order to implement optical XOR logic operation. Also, the proposed method provides more enhanced security strength than the conventional electronic OFB method due to the huge security key with 2-dimensional array. Finally, computer simulation results of encryption and decryption are shown to verify the proposed method, and hence the proposed method makes it possible to implement more effective and stronger optical block encryption system with high-speed performance and the benefits of parallelism.

• Journal of information and communication convergence engineering
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• v.16 no.3
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• pp.153-159
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• 2018

In this paper, we present a three-dimensional (3D) optical encryption technique for quick response (QR) code using computational synthesized integral imaging, computational volumetric reconstruction, and double random phase encryption. Two-dimensional (2D) QR code has many advantages, such as enormous storage capacity and high reading speed. However, it does not protect primary information. Therefore, we present 3D optical encryption of QR code using double random phase encryption (DRPE) and an integral imaging technique for security enhancement. We divide 2D QR code into four parts with different depths. Then, 2D elemental images for each part of 2D QR code are generated by computer synthesized integral imaging. Generated 2D elemental images are encrypted using DRPE, and our method increases the level of security. To validate our method, we report simulations of 3D optical encryption of QR code. In addition, we calculated the peak side-lobe ratio (PSR) for performance evaluation.

• Journal of Ubiquitous Convergence Technology
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• v.2 no.1
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• pp.12-17
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• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of Korea Multimedia Society
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• v.20 no.12
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• pp.1913-1927
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• 2017

Encryption technology is to hide information in a cyberspace built using a computer and to prevent third parties from changing it. If a malicious user accesses unauthorized device or application services on the Internet of objects, it may be exposed to various security threats such as data leakage, denial of service, and privacy violation. One way to deal with these security threats is to encrypt and deliver the data generated by a user. Encrypting data must be referred to a technique of changing data using a complicated algorithm so that no one else knows the content except for those with special knowledge. As computers process computations that can be done at a very high speed, current cryptographic techniques are vulnerable to future computer performance improvements. We designed and implemented a new encryption program that combines ancient and modern cryptography so that the user never knows about data management, and transmission. The significance of this paper is that it is the safest method to combine various kinds of encryption methods to secure the weaknesses of the used cryptographic algorithms.