• 한국초전도ㆍ저온공학회논문지
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• 제17권2호
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• pp.25-30
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• 2015

In order to realize economical applications, it is important to reduce the ac loss of 2G high-temperature superconductor coated conductors. It seems to be reasonable that a multi-filamentary wire can decrease the magnetization loss. In this study, we prepared two samples of YBCO coated conductors with striations. We measured local superconducting properties of both samples by using Low Temperature Scanning Laser and Hall Probe Microscopy (LTSLHPM). The distribution of the local critical temperature of samples was analyzed from experimental results of Low Temperature Scanning Laser Microscopy (LTSLM) near the superconducting transition temperature. According to LTSLM results, spatial distributions of the local critical temperature of both samples are homogeneous. The local current density and the local magnetization in samples were explored from measuring stray fields by using Scanning Hall Probe Microscopy (SHPM). From SHPM results, the remanent field pattern of the one bridge sample in an external magnetic field confirms the Bean's critical state model and the three bridge sample has similar remanent field pattern of the one bridge sample. The local magnetization curve in the three bridge sample was measured from external fields from -500 Oe to 500 Oe. We visualized that the distribution of local hysteresis loss are related in the distribution of the remanent field of the three bridge sample. Although the field dependence of the critical current density must be taken into account, the relation of the local hysteresis loss and the remanent field from Bean's model was useful.

• 한국초전도ㆍ저온공학회논문지
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• 제5권1호
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• pp.60-65
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• 2003

An effective modeling and simulation scheme of a resistive type Superconducting fault Current Limiter (SFCL) using PSCAD/EMTDC is proposed in this paper. In case of High Temperature Superconducting (HTS) resistive type fault current limiter current limiting is implemented by the ultra-fast transition characteristics from the superconducting (non-resistive) state to the normal (resistive) state by overstepping the critical current density. The states can generally be divided into three sub-states: the superconducting state the quench state and the recovery state respectively. In order to provide alternative application schemes of a resistive type SFCL, an effective modeling and simulation method of the SFCL is necessary. For that purpose, in this study, an actual experiment based component model is developed and applied for the simulation of the real resistive type SFCL using PSCAD/EMTDC. The proposed simulation scheme can be implemented to the grid system readily under various system conditions including sort of faults and the system capacity as well. The simulation results demonstrate the effectiveness of the proposed model and simulation scheme.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.25-31
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• 2005

Since the discovery of the high temperature superconductors many researches have been performed for the practical applications of superconductivity technologies in various fields. As results, significant progress has been achieved. Especially, Superconducting Fault Current Limiter (SFCL) offers an attractive means In limit fault current in power systems. HTS resistive type SFCL is based on the ultra fast transition from the superconducting (non resistive) state to the normal (resistive) state by overstepping the critical current density, In this study, the simulation method of resistive type superconducting fault current limiter using EMTDC is proposed and the developed EMTDC model of SFCL is applied to the modeled power network using the Parameters of real system.

• KIEE International Transactions on Electrophysics and Applications
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• 제5C권5호
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• pp.217-220
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• 2005

We have fabricated a superconducting YBCO system according to the pyrolysis method and low pressure apparatus. In our experiment, the X-ray diffraction pattern of the non doped YBaCuO layer indicated that the superconductor contained only 90K phase crystal. The critical temperature and critical current density for a thick layer at $650^{\circ}C$ were Tc=90 K and $Jc=6{\times}10^{4}A/cm^2$ at 90K. In low pressure apparatus, the 90 K phase YBaCuO was grown at a lower temperature compared with the normal system. Tc and Jc at $650^{\circ}C$ were Tc = 90 K and $Jc=6{\times}10^{4}A/cm^2$ at 90K.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.854-859
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• 2009

The YBCO coated conductor is an important element that forms the superconducting power equipment. The first advantage of applying YBCO coated conductor to superconducting power equipment is that it can effectively addresses the normal and fault currents using less quantity of wire than when using Bi tape due to its high critical current density. Second, it can limit the fault current fast because its index value is high. so that the resistance can be produced fast when it is applied to the superconducting current limiting element. Third, the type of stabilization layer that surrounds the YBCO superconductor is selectable and the magnitude of the resistance that is produced from quenching can be adjusted. This study researched into the manufacture of current-limiting element of using YBCO coated conductor, into the characteristics of current limiter that considered by combining the manufactured element with the resistive-type superconducting fault current limiter.

• Progress in Superconductivity
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• 제8권2호
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• pp.175-180
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• 2007

High temperature superconductor $YBa_2Cu_3O_{7-x}$ (YBCO) films have been grown by in-situ electron beam evaporation on artificial metal tapes such as ion-beam assisted deposition (IBAD) and rolling assisted biaxially textured substrates (RABiTS). Deposition rate of the YBCO films is $10{\sim}100{\AA}/sec$. X-ray diffraction shows that the films are grown epitaxially but have inter-diffusion phases, like as $BaZrO_3\;or\;BaCeO_3$, at their interfaces between YBCO and yttrium-stabilized zirconia (YSZ) or $CeO_2$, respectively. Secondary ion mass spectroscopy depth profile of the films confirms diffused region between YBCO and the buffer layers, indicating that the growth temperature ($850{\sim}900^{\circ}C$) is high enough to cause diffusion of Zr and Ba. The films on both the substrates show four-fold symmetry of in-plane alignment but their width in the -scan is around $12{\sim}15^{\circ}$. Transmission electron microscopy shows an interesting interface layer of epitaxial CuO between YBCO and YSZ, of which growth origin may be related to liquid flukes of Ba-Cu-O. Resistivity vs temperature curves of the films on both substrates were measured. Resistivity at room temperature is between 300 and 500 cm, the extrapolated value of resistivity at 0 K is nearly zero, and superconducting transition temperature is $85{\sim}90K$. However, critical current density of the films is very low, ${\sim}10^3A/cm^2$. Cracking of the grains and high-growth-temperature induced reaction between YBCO and buffer layers are possible reasons for this low critical current density.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
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• pp.236-242
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• 2000

NZP velocities were investigated on Ag sheathed multi filamentary Bi-2223 tape and direction type HTS cable. The critical current($I_c$) of Ag sheathed Bi-2223 tape and direction type HTS cable were 12 A, 63 A at 77 K, 0 T. NZP velocities of tape with two condition of DC and AC were almost same at each temperature. In case of DC, the NZP velocities of numerical analysis and experiment were almost same. NZP velocities of direction type HTS cable were 1.9-2.4 cm/sec. The result shows that the total transport current of spiral type HTS cable in $LN_2$ was 475[A], and transport current passed through almost the outer layer (2-layer). Also, AC transport losses in outer layer of HTS cable was proportion to $I^2$ and higher than losses of inner layer. And in case of $I_p=I_c$, calculated numerical loss density was concentrated on the edge of tape and most of loss density in cable was distributed outer layer more than inner layer.

• 한국가스학회지
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• 제6권1호
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• pp.92-97
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• 2002

가스흡수식 냉온수기의 작동매체로 사용되고 있는 LiBr 수용액 중에서 열교환기 세관용 재료인 동 세관 및 동합금재인 큐프로니켈 세관의 부식특성에 관한 연두를 하기 위하여 $62\%$ LiBr 수용액 중에서 각 재료에 대한 전기화학적 분극실험을 실시하여 부식특성을 고찰한 결과 다음과 같은 결론을 얻었다 1) 열교환기 세관재의 분극저항은 $30\%$ 큐프로니켈 세관 > $10\%$ 큐프로니켈 세관 > 동 세관의 순으로 높게 나타난다 2) 큐프로니켈 세관의 개로전위는 동 세관보다 귀전위화되면서 부식전류밑도는 더 억제된다 3) $30\%$ 큐프로니켈 세관의 부동태 영역은 $10\%$ 큐프로니켈 세관보다 전위구간이 더 크게. 나타나면서 부동태유지 전류밀도는 더 낮아진다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.375-375
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• 2009

For many large-scale applications of high-temperature superconducting materials, large critical current density($J_c$) in high applied magnetic fields are required. A number of methods have been reported to introduce artificial pinning centers(APCs) in $YBa_2Cu_3O_{7-\delta}$(YBCO) films for enhancement of their $J_c$. We report measurements of critical current in $YBa_2Cu_3O_{7-\delta}$ films deposited by PLD on $SrTiO_3$ substrates decorated with Au nanoparticles. Au nanoparticles were synthesized on STO substrates with self assembled monolayer. Microstructural analysis of the obtained YBCO films was performed by using cross-section transmission electron microscopy(TEM). Phase and textural analysis was done using X-ray diffraction. The surface morphology and surface roughness(Ra) of the layers was measured by atomic force microscopy(AFM).

• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.