• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2370-2378
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• 2009

The enhanced phase angle estimation algorithm is essential to supply the power stably under synchronizing with grid source. In this paper, we are proposed the novel phase angle estimation algorithm and verified the validity of proposed method as simulation with PSIM and experiments. We sort the harmonics element using high-pass filter(HPF) that have the cut-off frequency below basic element and make reverse d-q transformation. So, it can be restored the harmonics element at stationary axis, and we can get the fundamental voltage element of AC grid. Proposed PLL method have a rapid responsibility and a large margin at controller design than conventional method because it have a small phase delay and a sufficient controller gain margin. And, it can reduce the error of voltage rms value and axis transformation according to robust PLL algorithm against the harmonic and phase unbalance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.5
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• pp.789-796
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• 2008

This paper describes a single-phase active power filter based on a newly developed digital controller. The developed controller utilizes FFT(Fast Fourier Transform) algorithm to extract the reference signal from the load current, considering the phase-angle delay of each order of harmonics. Optimized technique was applied for whole control algorithm to implement the real-time operation of developed controller. The performance of developed controller for a single-phase active power filter was verified through computer simulations with PSCAD/EMTDC. The feasibility of hardware implementation was confirmed by building and testing a prototype. The developed digital controller for a single-phase active power filter can compensate the harmonic current generated by the power supply for digital equipment.

• Journal of Power Electronics
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• v.4 no.2
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• pp.102-111
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• 2004

This paper is concerned with a deadbeat current control implementation of shunt-type three-phase active power filter (APF). Although the one-dimensional deadbeat control method can attain time-optimal response of APF compensating current, one sampling period is actually required fur its settling time. This delay is a serious drawback for this control technique. To cancel such a delay and one more delay caused by DSP execution time, the desired APF compensating current has to be predicted two sampling periods ahead. Therefore an adaptive predictor is adopted for the purpose of both predicting the control error of two sampling periods ahead and bringing the robustness to the deadbeat current control system. By adding the adaptive predictor output as an adjustment term to the reference value of half a source voltage period before, settling time is made short in a transient state. On the other hand, in a steady state, THD (total harmonic distortion) of the utility grid side AC source current can be reduced as much as possible, compared to the case that ideal identification of controlled system could be made.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.11
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• pp.1560-1565
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• 2013

This paper proposes the control method for compensating for unbalanced grid current and reducing a total harmonic distortion (THD) of the grid current at the three-phase grid-connected inverter systems under unbalancd and distorted grid voltage conditions. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for a minimum point of THD. Both the gain and angle of a compensation voltage at the minimum point of THD of the grid current are derived. The negative-sequence components in the three-phase unbalanced grid voltage are cancelled in order to achieve the balanced grid current. The simulation and experimental results show the validity of the proposed control methods.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1151-1154
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• 2000

Phase angle control ac drives system gains a high popularity due to their simple implementation despite the disadvantage of their poor input power factor especially for large values of phase delay angle. Furthermore it generates subharmononic current at specific phase angle. As input current of do drive systems are sinusoidal, the power factor and subharmonic current characteristics are improve. This paper presents the application of a PWM control technique of do chopper system to reduce the subharmonic current and its characteristics using single-phase dc chopper drive system of universal motor.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.2
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• pp.107-114
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• 2014

This paper applies a compensated low pass filter (LPF) to current measurements for permanent magnet synchronous motor (PMSM) drives. The noise limits the bandwidth of current controllers and has more adverse influences on control performances under the light load condition because of the low signal-to-noise ratio. In order to eliminate the noise sensitivity, this paper proposes a digital LPF with a compensator of gain attenuation and phase delay which are unacceptable in current information for PMSM drives. Characteristics of the proposed LPF are analyzed in comparison with the general LPFs. The compensated LPF is basically designed by the orthogonal property of the measured currents in the ${\alpha}{\beta}$ stationary reference frame. In addition, an implementation issue of the proposed method is discussed. Experimental results using the proposed method show improvements of the current control performance from two perspectives, rapid step responses and reductions of harmonic distortion.

• Journal of Power Electronics
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• v.14 no.2
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• pp.392-401
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• 2014

A fast-transient repetitive control strategy for a three-phase shunt active power filter is presented in this study to improve dynamic performance without sacrificing steady-state accuracy. The proposed approach requires one-sixth of the fundamental period required by conventional repetitive control methods as the repetitive control time delay in the synchronous reference frames. Therefore, the proposed method allows the system to achieve a fast dynamic response, and the program occupies minimal storage space. A proportional-integral regulator is also added to the current control loop to eliminate arbitrary-order harmonics and ensure system stability under severe harmonic distortion conditions. The design process of the corrector in the fast-transient repetitive controller is also presented in detail. The LCL filter resonance problem is avoided by the appropriately designed corrector, which increases the margin of system stability and maintains the original compensation current tracking accuracy. Finally, experimental results are presented to verify the feasibility of the proposed strategy.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.1-8
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• 2012

The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.