• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1480-1482
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• 2005

The major causes of power quality deterioration are harmonic current through semiconductor switching device, due to use of nonlinear loads such as diodes rectifier or thyristor rectifiers. In response to this concerns, this paper presents a new control method of single-phase active power filter(APF) for the compensation of harmonic current components in nonlinear loads. In order to make the complex calculation to be possible, the single-phase system that has two phases was made by constructing a imaginary second-phase giving time delay to load currents. In the conventional method, a imaginary-phase lagged to the load current T/4(here T is the fundamental cycle) was made. But in this proposed method, the new signal, which has the delayed phase through the filter, using the phase-delay property of low-pass filter, was used as the second phase. As this control method is applied to the system of single phase, an instantaneous calculation was done rather by using the rotating reference frames that synchronizes with source-frequency than by applying instantaneous reactive power theory that uses the conventional fixed reference frames.

• 전기학회논문지P
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• 제62권1호
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• pp.12-17
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• 2013

Fault currents are expressed as a combination of harmonic components and exponentially decaying DC offset components, during the occurrence of fault in power system. The DC offset components are included, when the voltage phase angle of fault inception is closer to $0^{\circ}$ or $180^{\circ}$. The digital protection relay should be detected quickly and accurately during the faults, despite of the distortions of relaying signal by these components. It is very important to implement the robust protection algorithm, that is not affected by DC offset and harmonic components, because most relaying algorithms extract the fundamental frequency component from distorted relaying signal. So, In order to high performance in relaying, advanced DC offset removal filter is required. In this paper, a new DC offset removal filter, which is no need to preset a time constant of power system and accurately estimate the DC offset components with one cycle of data, is proposed, and compared with the other filter. In order to verify performance of the filter, we used collecting the current signals after synchronous machine modeling by ATPDraw5.7p4 software. The results of simulation, the proposed DC offset removal filter do not need any prior information, the phase delay and gain error were not occurred.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권5호
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• pp.249-257
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• 2002

In this paper, a novel control scheme compensating source voltage unbalance and harmonic currents for the combined system of series active and shunt passive power filter is proposed, where no low/high-pass filters are used in deriving the reference voltage for compensation. The phase angle and the reference voltages compensating for harmonic current and unbalanced voltage are derived from the positive sequence component of the unbalanced voltage set, which is simply obtained by using digital all-pass filters. In order to remove the phase delay in generating the reference voltage for compensation, the reference of 5th and 7th harmonic components is predicted one-sampling ahead. The validity of the proposed scheme has been verified for 3[kVA] proto-type active power filter system.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.94-100
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• 2008

This paper presents a new control method of single-phase active power filter (APF) for the compensation of harmonic current components in nonlinear loads. To facilitate the possibility of complex calculation for harmonic current detection of the single phase, a single-phase system that has two phases was constructed by including an imaginary second-phase giving time delay to the load current. The imaginary phase, which lagged the load current T/4 (Here T is the fundamental cycle) is used in the conventional method. But in this proposed method, the new signal as the second phase is delayed by the filter. Because this control method is applied to a single-phase system, an instantaneous calculation was developed by using the rotating reference frames synchronized to source-frequency rather than by applying instantaneous reactive power theory that uses the conventional fixed reference frames. The control scheme of single-phase APF for the current source with R-L loads is applied to a laboratory prototype to verify the proposed control method.

• Journal of Power Electronics
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• 제13권4호
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• pp.712-718
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• 2013

This paper proposes a control method for reducing the total harmonic distortion (THD) of the grid current of three-phase grid-connected inverter systems when the grid voltage is distorted. The THD of the grid current caused by grid voltage harmonics is derived by considering the phase delay and magnitude attenuation due to the hardware low-pass filter (LPF). The Cauchy-Schwarz inequality theory is used in order to search more easily for the minimum point of the THD. Both the gain and angle of the compensation voltage at the minimum point of the THD of the grid current are derived with the variation of cut-off frequencies of the hardware LPF. Simulation and experimental results show the validity of the proposed control methods.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.790-799
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• 2018

This paper proposes a single-phase unified power quality conditioner (S-UPQC) for maintaining power quality issues in a microgrid. The S-UPQC can compensate the voltage and current harmonics, voltage sag, and swell as a dynamic voltage restorer (DVR), regardless of variations in the grid frequency. Odd harmonics are treated as even-order harmonics in a rotating frame to implement the harmonic compensators with only one repetitive controller (RC) without any harmonic extractor. The dynamic performance is improved and the delay time is reduced in the RC. The S-UPQC control scheme is designed to maintain accurate and stable operation under deviations of the grid frequency by using the Lagrange interpolation-based finite-impulse-response (LIFIR) filter approximation method. The proposed control schemes were validated through a simulation and experiment.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.955-959
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• 2003

A technique for realizing linear phase IIR filters has been proposed by Powell-Chau which gives a real-time implementation of H(z-1).H(z), where H(z) is a causal nonlinear phase IIR filter. Powell-Chau system is linear but not timeinvariant system. Therefore, that system has group delay response that exhibits a minor sinusoidal variation superimposed on a constant value. In the signal processing, this oscillation seriously degrade the signal quality. Unfortunately, that system has a large sample delay of 4L and also more computational complexity. Proposed system is present a reduced computational complexity technique by moved the numerator polynomial of H(1/z) out to cascade with causal filter H(z) and remain only all-pole of H(1/z), then applied truncated infinite impulse response to finite with truncated IIR filtel $H_L$(z) and L sample delay to subtract the output sequence from the top and bottom filter. Proposed system is linear time invariance and group delay response and total harmonic distortion are also improved.

• 전력전자학회논문지
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• 제8권6호
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• pp.576-584
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• 2003

본 논문에서는 비 선형 단상부하에 의해 발생하는 전류 고조파를 보상하기 위한 단상능동전력필터의 새로운 제어방법을 제안한다. 부하전류에 시간지연을 주어 임의의 두 번째 상을 생성한 후 단상시스템을 두 상을 갖는 시스템으로 만들어 복소계산을 가능하게 한다. 기존의 방법은 부하전류를 1/4 T(T는 기본파의 주기) 만큼 지연시켜서 가상의 상을 만들었지만, 본 논문에서 제안하는 방법은 저역통과필터가 상 지연의 특성을 가지는 것을 이용하여 필터를 통과한 지연된 위상을 가진 새로운 신호를 두 번째 상으로 이용하였다. 두 개의 위상이 다른 상이 존재하므로 고조파 전류의 순시계산이 가능하게 된다. 기존의 고정좌표계를 이용하여 순시무효전력이론을 적용하지 않고, 본문에서는 전원주파수에 동기하는 회전좌표계를 사용하여 순시계산을 하였고, 보상전류 지령치를 구하였다. 전류원으로 사용되는 RL부하에 대하여 시뮬레이션과 실험을 수행하였고, 제안된 제어법의 유효성을 입증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• 한국통신학회논문지
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• 제32권2A호
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• pp.213-219
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• 2007

본 논문에서는 입력단에 위상 지연 선로와 하모닉 출력단에 $90^{\circ}$ 하이브리드 결합기를 사용하여 억압특성을 개선한 새로운 구조의 주파수 체배기를 설계 및 제작하였다. 제안된 구조의 주파수 체배기는 출력전력 결합특성과 기본주파수의 억압특성을 개선하였다. $2.13{\sim}2.15GHz$의 주파수를 2체배 하여 $4.26{\sim}4.30GHz$의 신호원을 얻는 능동주파수 2체배기이며, 입력전력이 10dBm일 때 0.79dB 변환이득과 기본주파수에서 -55.54dBc, 3체배 주파수 6.42GHz에서 -44.76dBc, 4체배 주파수 8.56GHz에서 -39.19dBc의 개선된 억압특성값 얻을 수 있었다.