• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

• Journal of Industrial Technology
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• v.27 no.B
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• pp.103-107
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• 2007

In this paper, the light screen sensing system is introduced and testified to detect small grains such as seeds or electronic chips of uneven sized. Two modules composed of transmitter-receiver sensor array and microprocessor-based sensor signal processing system are developed to realize the proposed system. Experimental results showed that the sensing signal was relatively clear and its counting performance was very stable.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.341-345
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• 1996

This paper presents the dynamics and the teal-time control of a horizontally rotating inverted pendulum. The dynamic equations representing three degrees of freedom rigid body motion of the pendulum are derived, and the state feedback controller is applied to the motion control of the pendulum. A 32 bit counter board with 16 bit hardware communication ability is developed to improve the real-time control performance and is applied to a horizontally rotating inverted pendulum. The simulation and experimental studies are conducted to evaluate the performance of the developed pendulum system and the timing in the real-time control is analyzed.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.591-594
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• 2005

This paper describes a design of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security. The CCMP core is designed with 128-bit data path and iterative structyre which uses 1 clock cycle per round operation. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 23% compared with conventional LUT-based design. The CCMP core designed in Verilog-HDL has 35,013 gates, and the estimated throughput is about 768Mbps at 66-MHz clock frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.290-295
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• 2005

The incremental encoder has been mostly used to measure the speed and position of the motor. As the output signals of encoder are high frequency digital signals, they have much influence on radiation noises due to switching of the power semiconductor circuits. It is so difficult to suppress the noises with the conventional LPF. In this paper, the hardware digital filter for suppressing noises in the output signals of the encoder signals is developed. As both the clock frequency and counter in the digital filter for encoder are easily adjusted according to the kinds of noises, any noises in the encoder can be entirely eliminated. The performance of the digital filter has been verified by simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.106-108
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• 2020

대부분의 최신 마이크로 프로세서에서 사용 가능한 하드웨어 퍼포먼스 카운터는 시스템과 어플리케이션의 상태를 모니터링, 분석 및 최적화하는 다양한 용도로 폭넓게 사용되고 있다. 적은 오버헤드로 시스템의 가장 기본적인 정보를 수집할 수 있기 때문에 다양한 분야에서 활용이 가능하다. 이러한 퍼포먼스 카운터는 리눅스에 내장되어 있는 퍼프 이벤트를 통하여 수집 할 수 있는데 클러스터 시스템에서는 단일 노드에서와는 다른 방법을 사용하여 이벤트를 수집해야 한다. 본 연구에서는 클러스터 시스템에서 하드웨어 퍼포먼스 카운터를 수집하는 방법과 오버헤드에 대하여 연구하여 카운터의 활용을 지원하고자 한다.