• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.10-11
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• 2014

In a 2-dimensional (2D) Discrete Cosine Transform (DCT) hardware, a significant fraction of the total hardware area is contributed by the combinational logic used to perform 1-dimensional (2D) transform. The size of the non-combinational logic i.e. the transpose memory is dictated by the size of the largest transform supported. Hence, the optimization of hardware area is performed mainly for 1D-transform combinational logic. This paper demonstrates the use of Multiple Constant Multiplication (MCM) algorithm to reduce the combinational logic area. Partial optimizations are also described for the cases where the direct use of MCM algorithm doesn't meet the timing constraint. Experimental results show that 46% improvement in gate count is achieved for 32 point 1D DCT transform logic after using MCM optimization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.454-468
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• 1997

This paper presents a bitwidth optimization algorithm for efficient hardware sharing in digital signal processing system. The proposed algorithm determines the fixed-point representation for each signal through bitwidth optimization to generate the hardware requiring less area. To reduce the operator area, the algorithm partitions the abstract operations in the design description into several groups, such that the operations in the same group can share an operator. The partitioning result are fed to a high-level synthesis system to generate the pipelined fixed-point datapaths. The proposed algorithm has been implemented in SODAS-DSP an automatic synthesis system for fixed-point DSP hardware. Accepting the models of DSP algorithms in schematics, the system automatically generates the fixed-point datapath and controller satisfying the design constraints in area, speed, and SNR(Signal-to-Noise Ratio). Experimental results show that the efficiency of the proposed algorithm by generates the area-efficient DSP hardwares satisfying performance constraints.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.3
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• pp.133-144
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• 2000

Genetic Algorithm(GA) has been known as a method of solving large-scaled optimization problems with complex constraints in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementations of Genetic Algorithm Processors(GAP) are focused on in recent studies. In this paper, a hardware-oriented GA was proposed in order to save the hardware resources and to reduce the execution time of GAP. Based on steady-state model among continuos generation model, the proposed GA used modified tournament selection, as well as special survival condition, with replaced whenever the offspring's fitness is better than worse-fit parent's. The proposed algorithm shows more than 30% in convergence speed over the conventional algorithm in simulation. Finally, by employing the efficient pipeline parallelization and handshaking protocol in proposed GAP, above 30% of the computation speed-up can be achieved over survival-based GA which runs one million crossovers per second (1㎒), when device speed and size of application are taken into account on prototype. It would be used for high speed processing such of central processor of evolvable hardware, robot control and many optimization problems.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.10
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• pp.1314-1325
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• 1995

In this paper, we describe hardware implementation of VSB (Vestigial SideBand) mo-dulation equalization systems for HDTV (High Definition TeleVision). By modifying an adaptive equalization algorithm, we propose a hardware architecture with a low hardware cost and the performance close to floating-point operations. We also employ the pipeline concept to reduce the hardware cost. The effectiveness of the proposed hardware architecture is de- monstrated through computer simulation and the optimization result of VHDL circuit descriptions.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.4
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• pp.779-787
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• 2010

In this paper, We introduce electrical tracking generated from surface activity associated with flow of leakage current on insulator under wet and contaminated conditions and design electrical tracking pattern recognition system by using LabVIEW. We measure the leaking current of contaminated wire by using LabVIEW software and the NI-c-DAQ 9172 and NI-9239 hardware. As pattern recognition algorithm and optimization algorithm for electrical tracking system, neural networks, Radial Basis Function Neural Networks(RBFNNs) and particle swarm optimization are exploited. The designed electrical tracking recognition system consists of two parts such as the hardware part of electrical tracking generator, the NI-c-DAQ 9172 and NI-9239 hardware and the software part of LabVIEW block diagram, LabVIEW front panel and pattern recognition-related application software. The electrical tracking system decides whether electrical tracking generate or not on electrical wire.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.644-645
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• 2021

In this paper, we propose a hardware structure of a watermarking processor based on deep learning technology to protect the intellectual property rights of ultra-high resolution digital images and videos. We propose an optimization methodology to implement a deep learning-based watermarking algorithm in hardware.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.86-93
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• 2004

The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.42-45
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• 2012

A network processor (NP) is an application-specific instruction-set processor for fast and efficient packet processing. There are many issues in compiler's code generation and optimization due to NP's hardware constraints and special hardware support. In this paper, we describe in detail how to resolve the issues. Our compiler was developed on LLVM 3.0 and the NP target was our in-house network processor which consists of 32 64-bit RISC processors and supports multi-context with special hardware structures. Our compiler incurs only 9.36% code size overhead over hand-written code while satisfying QoS, and the generated code was tested on a real packet processing hardware, called S20 for code verification and performance evaluation.

• Smart Media Journal
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• v.11 no.2
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• pp.70-76
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• 2022

IoT application development using a cloud server causes problems such as data transmission and reception delay, network traffic, and cost for real-time processing support in network connected hardware. To solve this problem, edge cloud-based platforms can use neuromorphic hardware to enable fast data transfer. In this paper, we propose a model optimization method for supporting spiking neural networks on FPGA hardware. We focused on auto-adjusting network model parameters optimized for neuromorphic hardware. The proposed method performs optimization to show higher performance based on user requirements for accuracy. As a result of performance analysis, it satisfies all requirements of accuracy and showed higher performance in terms of expected execution time, unlike the naive method supported by the existing open source framework.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.