• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.2179-2189
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• 1998

This paper presents the methodolog~- to improve the computatIon efficiency of the simulation by developing the concept of the dynamic preservatIon and reurilization of the state transitions. The computation COst is emormous for the simulation of hardware described in hardware description languages including VHDL Analyzing the process of simulation precisely, we have found that the number of the pattems for the state transition is limited if the sizes of hardware modules are determined properly. The pattems are preserved dynamically when they appeared first, and are utilized in later simulation in order to reduce the simulation costs. In this study, the efficiency of the present method was verified using case studies for the simulation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.12
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Journal of Broadcast Engineering
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• v.26 no.7
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• pp.855-861
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• 2021

Neural Architecture Search (NAS) is cutting-edge technology in the machine learning community. NAS Without Training (NASWOT) recently has been proposed to tackle the high demand of computational resources in NAS by leveraging some indicators to predict the performance of architectures before training. The advantage of these indicators is that they do not require any training. Thus, NASWOT reduces the searching time and computational cost significantly. However, NASWOT only considers high-performing networks which does not guarantee a fast inference speed on hardware devices. In this paper, we propose a multi objectives reward function, which considers the network's latency and the predicted performance, and incorporate it into the Reinforcement Learning approach to search for the best networks with low latency. Unlike other methods, which use FLOPs to measure the latency that does not reflect the actual latency, we obtain the network's latency from the hardware NAS bench. We conduct extensive experiments on NAS-Bench-201 using CIFAR-10, CIFAR-100, and ImageNet-16-120 datasets, and show that the proposed method is capable of generating the best network under latency constrained without training subnetworks.

• Smart Media Journal
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• v.11 no.2
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• pp.70-76
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• 2022

IoT application development using a cloud server causes problems such as data transmission and reception delay, network traffic, and cost for real-time processing support in network connected hardware. To solve this problem, edge cloud-based platforms can use neuromorphic hardware to enable fast data transfer. In this paper, we propose a model optimization method for supporting spiking neural networks on FPGA hardware. We focused on auto-adjusting network model parameters optimized for neuromorphic hardware. The proposed method performs optimization to show higher performance based on user requirements for accuracy. As a result of performance analysis, it satisfies all requirements of accuracy and showed higher performance in terms of expected execution time, unlike the naive method supported by the existing open source framework.

• KIEAE Journal
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• v.6 no.1
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• pp.3-10
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• 2006

As has been expected, economic factors are a major consideration in almost every decision in building design process. Assuming that improving a lighting system, existing or proposed, will reduce operating cost, what preliminary economic guidelines can be established to determine whether any proposed investment appears cost effective? In such a case a reasonable technique to compare system costs is by life-cycle costing. Stated simply, a life-cycle cost represents the total cost of a system over its entire life cycle, that is, the sum of first cost and all future costs. This paper aims to exemplify the benefit of daylighting in term of economic consideration. Four different electric lighting system designs are proposed and a lighting control system that is continuously operating according to the level of daylight in the space has been adapted. The accumulated performance of electric and daylighting is figured out to declare the effective depth of daylight in the space. The analysis on the saving amount of lighting energy due to daylight has been undertaken in answer to the question, that is, several projects are being considered, which is the most desirable from the cost-effectiveness viewpoint. The result shows clearly that although denser layout of lighting fixtures might be more effective to interface to the level of daylight ceaselessly changeable, its economic benefit may not meet the expected criterion the reason of increased initial investment and maintenance cost for the fixtures and control hardware.

• The Journal of Asian Finance, Economics and Business
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• v.9 no.4
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• pp.93-98
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• 2022

The article analyzes the impact of factors affecting the use of cost information is examined, which adds to the empirical evidence on the factors affecting the use of cost information in Vietnam's seafood processing firms. 58 seafood processing firms in Vietnam were surveyed using a questionnaire survey of all levels of management, chief accountants, and accountants. A total of 235 questionnaires were gathered for the survey. Because many of the surveys were invalid due to empty cells, the author selected to use 214 questionnaires. The 5-level Likert scale is familiarly used in many studies, so the author also quantifies each factor according to five levels. Quantitative research was carried out with SPSS 25 software. Research results show that 4 factors The function of cost information, cost management, information technology, and management support in the seafood processing industry in Vietnam all have a positive impact on the use of cost information. The author has provided recommendations based on the research findings to expand the use of cost information, consequently helping to improve the performance of Vietnamese seafood processing businesses. Managers must improve a variety of resources, including facilities (software, hardware), people (in-depth training on CAS for administration), departmental awareness, and UCI's ability to assess responsibility and reward in the organization.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.105-111
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• 2004

This paper describes the design of navigation system for an unmanned target drone which is operated by Korean army as for anti-air gun shooting training. Current target drone is operated by pilot control of on-board servo motor via remote control system. Automatic flight control system for the target drone greatly reduces work load of ground pilot and can increase application area of the drone. Most UAVs being operated nowdays use high-priced sensors as AHRS and IMU to measure the attitude, but those are costly. This paper introduces the development of low-cost automatic flight control system with low-cost sensors. The integrated automatic flight control system has been developed by integrating combining power module, switching module, monitoring module and RC receiver as an one module. The performance of navigation for low cost unmanned aerial vehicle, unmanned target drone as our test bed in this paper is verified by both Hardware in the loop simulation(HILS) to test performance of GPS as GPS output frequency high and results of flight test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• Proceedings of the KSRS Conference
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• 1999.11a
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• pp.25-30
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• 1999

This paper covers the development of a highly portable and low cost SPOT image data receiving system. We followed two design approaches. One is the software-based approach by which most of the real-time processing is handled by software. With the complete software-based design, it is simple to add a function for receiving any additional satellite data. Satellite-specific format handlers including error correction, decompression and decryption can easily be accommodated. On the other approach. we used a general hardware platform, IBM-PC and a low cost SCSI RAID (Redundant Away of Independent Disks), and therefore, we can make a low cost system.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.