• Title/Summary/Keyword: hardware cost

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Analysis of the Causes of Defects in Fenestration Construction and Their Impacts on Construction Quality - Focused on Door Hardware - (창호철물공사 하자발생 원인과 시공품질 영향분석에 관한 연구 - 문(Door)에 사용되는 창호철물 중심으로 -)

  • Moon, Sang-Deok;Chung, Jae-Min;Ock, Jong-Ho
    • Journal of the Korea Institute of Building Construction
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    • v.13 no.4
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    • pp.341-350
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    • 2013
  • For this study, a series of interviews with engineers in the Korean construction industry was carried out through a formal workshop format to analyze the causes of the inferior quality of builders' hardware. The authors established the causes of defects in window hardware construction in relation to the three aspects of system, design, and construction as involving the following seven factors: lack of system (including low ability to create construction specifications); low social awareness of the importance of window hardware; low technical capability to create design drawings; low design costs; small manufacturing capacity; low construction cost; and short duration of construction. Among the seven causes, the biggest cause of defects in window hardware construction is the lack of a system (low ability to create construction specifications), followed by low technical capability to create design drawings. In addition, this study carried out basic research to create measures to prevent defects in window hardware construction by analyzing how such causes of defects are distributed depending on the scale of architectural firms and construction companies during actual projects.

A low-cost compensated approximate multiplier for Bfloat16 data processing on convolutional neural network inference

  • Kim, HyunJin
    • ETRI Journal
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    • v.43 no.4
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    • pp.684-693
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    • 2021
  • This paper presents a low-cost two-stage approximate multiplier for bfloat16 (brain floating-point) data processing. For cost-efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low-cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well-known pre-trained models for the ImageNet database. Therefore, our design allows low-cost CNN inference systems with high test accuracy.

Design and Implementation of Soft masking method for IC card (IC카드를 위한 Soft masking 방법의 설계 및 구현)

  • 전용성;주홍일;전성익
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.107-110
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    • 2002
  • Soft masks mean that part or all of the program code for operating system or applications are located in the EEPROM or flash ROM. Since Soft masks allow errors to be corrected and programs to be modified quickly and at minimal cost, they are used primarily during testing and in the field trials. This paper introduces a hardware architecture of IC card for soft masks. We suggest a new down loading scheme for soft-mask ROM connected by an I/O interface. This scheme saves the new IC card development cost and time.

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A Study on the Development of HILS System for Performance Test of Digital Governor (디지털 조속기의 성능 시험을 위한 HILS 시스템 개발에 관한 연구)

  • 장민규;조성훈;전일영;안병원;박영산;배철오;이성근;김윤식
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.05a
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    • pp.317-319
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    • 2003
  • HILS(Hardware In-the Loop Simulation) is commonly used in the development and testing of embedded systems, when those systems cannot be tested easily, thoroughly, and repeated in their operational environments. HILS can be a useful tool to develop products more quickly and cost effectively and also reduces the possibility of serious defects being discovered after production. During the product development period, Design optimization and hardware/software debugging can be performed using HILS skill. This paper describes a HILS model for the STG(Steam-Turbine Generator) Simulator to prove the performance of the developed Digital Governor. It is developed using software technics which can confirm the responses of a real-time system.

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A Fully Synthesizable Bluetooth Baseband Module for a System-on-a-Chip

  • Chun, Ik-Jae;Kim, Bo-Gwan;Park, In-Cheol
    • ETRI Journal
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    • v.25 no.5
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    • pp.328-336
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    • 2003
  • Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

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An Investigation of Vehicle-to-Vehicle Distance Control Laws Using Hardware-in-the Loop Simulation (Hardware-in-the Loop Simulation 을 통한 차간거리 제어시스템의 제어 성능 연구)

  • Yi, Kyong-Su;Lee, Chan-Kyu
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.26 no.7
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    • pp.1401-1407
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    • 2002
  • This paper represents an investigation of the vehicle-to-vehicle distance control system using Hardware-in-the-Loop Simulation(HiLS). Control logic is primarily developed and tested with a specially equipped test vehicle. Establishment of an efficient and low cost development tool is a very important issue, and test vehicle approach is costly and time consuming. HiLS method is useful in the investigation of driver assistance and active safety systems. The HiLS system consists of a stepper motor for throttle control, a hydraulic brake system with an electronic vacuum booster, an electronic controller unit, a data logging computer which are used to save vehicle states and signals of actuator through a CAN and a simulation computer using mathematical vehicle model. Adaptation of a CAN instead of RS-232 Serial Interface for communication is a trend in the automotive industry. Since this environment is the same as a test vehicle, a control logic verified in laboratory can be easily transferred to a test vehicle.

An Efficient Processor Synchronization Scheme on Shared Memory Multiprocessor (공유메모리 다중처리기에서 효율적인 프로세서 동기화 기법)

  • 윤석한;원철호;김덕진
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.5
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    • pp.683-692
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    • 1995
  • Many kinds of large scale multiprocessing and parallel-processing systems have recently been developed. The contention on the shared data caused by multiple processors may degrade system performance. So, processor synchronization has become one of the important issues in these systems. To solve the synchornization issues, a lot of software and hardware schemes based on spin lock have been proposed. Although software schemes are easy to implement, hardware schemes are preferred in many systems to gain optimized performance. This paper proposes an efficient processor synchronization scheme, called QCX,and describes its design considerations, hardware, algorithm, protocol. Also, in this paper, the performance of QCX has been evaluated with QOLB[5] and LBP[7] using a simulation. The simulation, with varying the number of processor and the contention on shared variables, measured the average execution times of a workload. The simulation results show that the performances of QCX is best when practicability is considered. QCX is more efficient than QOLB and LBP in two aspects. First, the hardware of QCX is more simple and cost-effective because the cache structure need not be changed. Secondly, QCX is more general because it uses a generic atomic instruction.

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Low Cost Small CMG Performance Test and Analysis (저가 소형 CMG 성능시험 및 분석)

  • Rhee, Seung-Wu;Kwon, Hyoek-Jin
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.39 no.6
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    • pp.543-552
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    • 2011
  • Control Moment Gyro(CMG) is one of the most efficient momentum exchange devices for satellite attitude control and CMG is very essential device for agile satellite. In this study, the essential dynamic equation for the design of gimbal motor and wheel motor is summarized. The development process of SGCMG hardware for agile small satellite system, the description of developed hardware and its performance test results are presented. Test result shows that the developed hardware model can produce an output torque more than 1.2Nm as designed. Other test items are max. torque, gimbal bandwidth, minimum torque, torque error, gimbal rate error.

Virtual Experimental Kit for Embedded System Education (임베디드 시스템 교육을 위한 가상 실습 키트)

  • Cho, Sang-Young
    • The Journal of the Korea Contents Association
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    • v.10 no.1
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    • pp.59-67
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    • 2010
  • Laboratory works for embedded system courses are usually performed with hardware based experimental kits that equipped with an embedded board and software development tools. Hardware-based kits have demerits such as high initial setup cost, burdensome maintenance, inadaptability to industry evolution, and restricted educational outcomes. This paper proposes using virtual experimental environments to overcome the demerits of hardware-based kits and describes the design and implementation of a simulation-based virtual experimental kit. With ARM's ARMulator, we developed the kit by adding hardware IPs and user interface modules for peripherals. The developed kit is verified with an experimental program that uses all the augmented software modules. We also ported MicroC/OS-II on the virtual experimental kit for real-time OS experiments.

Hardware Architecture of Automatic Exposure Algorithm for CMOS Image Sensor (CMOS Image Sensor용 자동노출 알고리즘의 하드웨어 구조)

  • Mo, Sung-Wook;Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.7
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    • pp.1497-1502
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    • 2009
  • AE(Auto exposure) is a function to maintain the exposure value of a captured image constant, and is one of the crucial functionalities of a CIS-based mobile camera. Generally AE is implemented in software, requiring a CPU and a ROM to store the corresponding software. This approach increases the hardware size at the cost of increased flexibility. In this paper, we propose an AE algorithm featuring variable frame-rate and adaptive analog gain control, as well as a FSM-based hardware architecture for a CIS-based mobile camera.