• 전자공학회논문지A
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• 제33A권7호
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• pp.261-268
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• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• Journal of Information Processing Systems
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• 제15권6호
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• pp.1406-1421
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• 2019

The Internet-of-Things (IoT) has been deployed in almost every facet of our day to day activities. This is made possible because sensing and data collection devices have been given computing and communication capabilities. The devices implement System-on-Chips (SoCs) that incorporate a lot of functionalities, yet they are severely constrained in terms of memory capacitance, hardware area, and power consumption. With the increase in the functionalities of sensing devices, there is a need for low-cost synthesizable processors to handle control, interfacing, and error processing. The first step in selecting a synthesizable processor core for low-cost devices is to examine the hardware resource utilization to make sure that it fulfills the requirements of the device. This paper gives an analysis of the hardware resource usage of ten synthesizable processors that implement the Reduced Instruction Set Computer Five (RISC-V) Instruction Set Architecture (ISA). All the ten processors are synthesized using Vivado v2018.02. The maximum frequency, area, and power reports are extracted and a comparison is made to determine which processor is ideal for low-cost hardware devices.

• 전자공학회논문지B
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• 제32B권10호
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• pp.1314-1325
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• 1995

In this paper, we describe hardware implementation of VSB (Vestigial SideBand) mo-dulation equalization systems for HDTV (High Definition TeleVision). By modifying an adaptive equalization algorithm, we propose a hardware architecture with a low hardware cost and the performance close to floating-point operations. We also employ the pipeline concept to reduce the hardware cost. The effectiveness of the proposed hardware architecture is de- monstrated through computer simulation and the optimization result of VHDL circuit descriptions.

• International Journal of Advanced Culture Technology
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• 제7권4호
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• pp.313-320
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• 2019

Nowadays, as the availability of tiny, low-cost microcomputer increases at a high level, mobile robots are experiencing remarkable enhancements in hardware design, software performance, and connectivity advancements. In order to control Turtlebot 2, several algorithms have been developed using the Robot Operating System(ROS). However, ROS requires to be run on a high-cost computer which increases the hardware cost and the power consumption to the robot. Therefore, design an algorithm based on low-cost hardware is the most innovative way to reduce the unnecessary costs of the hardware, to increase the performance, and to decrease the power consumed by the computer on the robot. In this paper, we present a path-finding algorithm for TurtleBot 2 based on low-cost hardware. We implemented the algorithm using Raspberry pi, Windows 10 IoT core, and RPLIDAR A2. Firstly, we used Raspberry pi as the alternative to the computer employed to handle ROS and to control the robot. Raspberry pi has the advantages of reducing the hardware cost and the energy consumed by the computer on the robot. Secondly, using RPLIDAR A2 and Windows 10 IoT core which is running on Raspberry pi, we implemented the path-finding algorithm which allows TurtleBot 2 to navigate from the starting point to the destination using the map of the area. In addition, we used C# and Universal Windows Platform to implement the proposed algorithm.

• 산업경영시스템학회지
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• 제34권3호
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• pp.49-56
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• 2011

Estimating optimum hardware capacity of an e-learning system is very important process to grasp reasonable size of designing technique architecture and budget during step of ISP(information strategic planning) and development. It hugely influences cost and quality of the whole project. While investment on information system hardware has been continuously increased, there was no certified hardware capacity estimating method in e-learning system development. A guideline for hardware sizing of information systems was established by Telecommunication Technology Association in 2008. However, the guideline is not appropriate for estimating optimum hardware capacity of an e-learning system because it was designed to provide general standards for estimating hardware capacity of various types of projects. The purpose of this paper is to provide a methodology for estimating optimum hardware capacity in e-learning system development. To develop the methodology, this study, first of all, analyzes two e-learning development projects, in which the guideline was applied to estimate optimum hardware capacity. Then, this study finds out several key factors influencing on hardware capacity. Finally, this study suggests a methodology for estimating optimum hardware capacity of an e-learning system, in which weights for the factors are determined through AHP analysis.

• 한국정보통신학회논문지
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• 제23권12호
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• pp.1742-1745
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• 2019

Hidden flame detection after allegedly extinguishing a fire cannot be emphasized enough. There are a few commercial hidden fire detection equipments which are imported, but the cost is relatively high. In this contribution, we propose a development of a low-cost, high-performance hidden flame detector using open-source hardware/software. We use Raspberry-pi based hardware board equipped with a TFT touch-screen LCD, a 3G modem, and an attachable battery device altogether integrated in a plastic case fabricated with a 3D printer. The proposed hidden flame detector shows the same performance of a commercial product FLIR E5 while consuming less than a half of the cost.

• 한국국방경영분석학회지
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• 제27권1호
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• pp.10-27
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• 2001

This paper deals with the application of PRICE model in estimating the proper acquisition cost for weapon budgeting phase. The PRICE(Parametric Review of Information for Costing and Evaluation) Hardware model is a computerized method for deriving cost estimates of electronic and mechanical hardware assemblies and systems. The model can be used in obtaining not only initial cost estimates in conceptual phase, but also detailed cost estimates in budgeting phase depending on available historical and empirical data. We analyzed first step cost estimate parameters and derived cost equations using PRICe output dta. Using weight and complexity, We can find cost variation. Sensitivity analysis shows that cost increases exponentially as complexity increases exponentially as complexity increases. We estimated KAAV\`s (Korea Amphibious Assault Vehicle) production cost using the PRICE model and compare with engineering cost estimates which is based on actual production data submitted by the production company. The result shows that tow estimates are close within $\pm2%$ differences.

• 스마트미디어저널
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• 제9권3호
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• pp.116-121
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• 2020

Digital Information Display와 KIOSK는 전용 컨텐츠의 개발 비용으로 인한 초기 도입 비용 및 유지 비용과 제품의 특성으로 인해 설치 비용이 높다는 문제가 있다. 이러한 문제를 해결하기 위해 오픈소스 하드웨어 및 이벤트 기반 논 블로킹 I/O 알고리즘을 사용하여 음성 전송 시스템을 설계하고 구현하였다. 제안하는 오픈 하드웨어를 통한 음성송출 시스템은 시스템 초기 도입 비용과 유지 보수비용이 저렴하고, 다양한 형태로 활용할 수 있어서 정보 취약 계층의 정보에 대한 접근성을 향상할 수 있다.

• 전기전자학회논문지
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• 제15권1호
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• pp.10-14
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• 2011

In this paper, we present an efficient hardware architecture of unrolling image mapper of catadioptric omnidirectional imaging systems. The catadioptric omnidirectional imaging systems generate images of 360 degrees of view and need to be transformed into panorama images in rectangular coordinate. In most application, it has to perform the panorama unrolling in real-time and at low-cost, especially for high-resolution images. The proposed hardware architecture adopts a software/hardware cooperative structure and employs several optimization schemes using look-up-table(LUT) of coordinate conversion. To avoid the on-line division operation caused by the coordinate transformation algorithm, the proposed architecture has the LUT which has pre-computed division factors. And then, the amount of memory used by the LUT is reduced to 1/4 by using symmetrical characteristic compared with the conventional architecture. Experimental results show that the proposed hardware architecture achieves an effective real-time performance and lower implementation cost, and it can be applied to other kinds of catadioptric omnidirectional imaging systems.

• 한국정보통신학회논문지
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• 제24권8호
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• pp.1109-1112
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• 2020

This paper presents a low cost hardware message passing engine of enhanced atomic pipelined broadcast based on processing node status. In this algorithm, the previous atomic pipelined broadcast algorithm is modified to reduce the waiting time until next broadcast communication. For this, the processor change the transmission order of processing nodes based on the nodes' communication channel. Also, the hardware message passing engine architecture of the proposed algorithm is modified to be adopted to multi-core processor. The synthesized logic area of the proposed hardware message passing engine was reduced by about 16%, compared by the pre-existing hardware message passing engine.