• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1870-1883
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• 1993

In this paper, in order to build up the User Network Interface based on ATM, a study on traffic control techniques which should be performed by main function groups-B 75,5 NT2, LEX-is discussed. The structure of B-NT2 which is the most important function group In the User Network Interface is defined in quite a simple manner in addition, the functional blocks of LEX are defined in a similar manner as those of B NT2. It is possible to distribute total traffic control functions by using the similarities between B-NT2 and LEX and by allocating virtual path identifiers fixedly according to the characteristics of the traffics. For the traffic control techniques of ATM, relations among Connection Admtsslon Control, Usage Parameter Control and Bandwidth Allocation Control are defined and Multi Rule Base structure to realize optimal control functions according to the characteristics of the source traffics is proposed. And the Real-time Variable Window algorithmsimply designed to be suitable for the Multi Rule Base architecture is also proposed. The performances of the proposed algorithm are analyzed through the computer simulation by generating on-off source traffic in a virtual system that has the form of the proposed hardware. The analyzed results show that the distributed control is possible and that the implementation of the proposed architecture and algorithm is possible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1515-1527
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• 2016

With the growth of big data, machine learning, and cloud computing, the importance of storage that can store large amounts of unstructured data is growing recently. So the commodity hardware based distributed file systems such as MAHA-FS, GlusterFS, and Ceph file system have received a lot of attention because of their scale-out and low-cost property. For the data fault tolerance, most of these file systems uses replication in the beginning. But as storage size is growing to tens or hundreds of petabytes, the low space efficiency of the replication has been considered as a problem. This paper applied erasure coding data fault tolerance policy to MAHA-FS for high space efficiency and introduces VDelta technique to solve data consistency problem. In this paper, we compares the performance of two file systems, MAHA-FS and GlusterFS. They have different IO processing architecture, the former is server centric and the latter is client centric architecture. We found the erasure coding performance of MAHA-FS is better than GlusterFS.

• Journal of the Korean Institute of Landscape Architecture
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• v.43 no.5
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• pp.87-99
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• 2015

Prior hardware-centered rural development projects implemented top-down rural community regeneration via the local government in accordance with central government agency policies. To improve this, software-centered projects have been promoted since 2000. With central agency-led rural development projects changing into local government-led ones, rural community regeneration has been built per village. Although rural community regeneration projects appear to have implemented a bottom-up development currently, the top-down development procedures being facilitated by the intervention of administrative institutions have not disappeared. In this regard, the purpose of this research thesis is to effectively perform bottom-up development methods that go one step further from the current process of rural community regeneration. As the research site, this thesis selected Geochang, which has difficulties in being steadily maintained and operated despite the development of various rural community regeneration projects. Subsequently, it determined the current status and substantial analysis of a project of the rural community regeneration in Geochang through 1:1 interviews with civil servants in charge of administration as well as conducted a prior study on rural resident awareness of rural community regeneration through a survey of village head members and in-depth interviews with rural residents. Based on these data, a 10 times-round table conference was held under the participation of pertinent civil servants, professionals and rural residents to select practical strategies for cooperative rural community regeneration in Geochang as five key areas: local food, culture & welfare, rural villages, community development, and urban and rural interchanges. In addition, it is considered that the project of building villages must be implemented by establishing steadfast administrative co-operation systems, strengthening rural residents' participation capacities and supporting professionals' systemic integrated operation and maintenance. By doing so, this research thesis sought to determine practical strategies in the cooperative rural community regeneration in Geochang. It is expected that bottom-up development rural community regeneration will be built and introduced in each rural community in the future.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.53-58
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• 2005

The use of computers for control and monitoring of industrial process has expanded greatly in recent years. The computer used in such applications is shared between a certain number of time-critical control and monitor function and non time-critical batch processing job stream. Embedded systems encompass a variety of hardware and software components which perform specific function in host computer. Many embedded system must respond to external events under certain timing constraints. Failure to respond to certain events on time may either seriously degrade system performance or even result in a catastrophe. In the design of real-time embedded system, decisions made at the architectural design phase greatly affect the final implementation and performance of the system. Flexibility indicates how well a particular system architecture can tolerate with respect to satisfying real-time requirements. The degree of flexibility of real-time system architecture indicates the capability of the system to tolerate perturbations in timing related specifications. Given degree of flexibility, one may compare and rank different implementations. A system with a higher degree of flexibility is more desirable. Flexibility is also an important factor in the trade-off studies between cost and performance. In this paper, it is identified the need for flexibility function and shows that the existing real-time analysis result can be effective. This paper motivated the need for a flexibility for the efficient analysis of potential design candidates in the architectural design exploration or real time embedded system.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.3
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• pp.178-192
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• 2006

The buffer overflow attack is the single most dominant and lethal form of security exploits as evidenced by recent worm outbreaks such as Code Red and SQL Stammer. In this paper, we propose microarchitectural techniques that can detect and recover from such malicious code attacks. The idea is that the buffer overflow attacks usually exhibit abnormal behaviors in the system. This kind of unusual signs can be easily detected by checking the safety of memory references at runtime, avoiding the potential data or control corruptions made by such attacks. Both the hardware cost and the performance penalty of enforcing the safety guards are negligible. In addition, we propose a more aggressive technique called corruption recovery buffer (CRB), which can further increase the level of security. Combined with the safety guards, the CRB can be used to save suspicious writes made by an attack and can restore the original architecture state before the attack. By performing detailed execution-driven simulations on the programs selected from SPEC CPU2000 benchmark, we evaluate the effectiveness of the proposed microarchitectural techniques. Experimental data shows that enforcing a single safety guard can reduce the number of system failures substantially by protecting the stack against return address corruptions made by the attacks. Furthermore, a small 1KB CRB can nullify additional data corruptions made by stack smashing attacks with only less than 2% performance penalty.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.39-47
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• 2010

This paper proposes a numerical analysis to prove that the performance of the differential phase detections (DPDs) with the decision feedback, such as the decision feedback DPD (DF-DPD) and the DPD with recursively generated phase reference (DPD-RGPR), approach the performance of the coherent detection with differential decoding. The conventional differential phase detection for M-ary DPSK can make the receiver architecture simple, while it can make the bit-error rate (BER) performance poor because of the previous noisy phase as a reference phase. To improve the BER performance of the conventional differential detection, multiple symbol differential detection methods, including DF-DPD and DPD-RGPR, have been proposed. However, the studies on the analysis and on the comparison of these methods have been little performed. Then, this paper mathematically intends to analyze and compare the performance of the DPDs with the decision feedback. The analysis results show that the DPDs with the decision feedback can have the performance equal to that of the coherent detection with differential decoding and be available for the noncoherent detection in the improved performance. Considering the hardware complexity, the DPD RGPR with the simple detection process by using the recursively generated phase reference can be more simply implemented than the DF-DPD based on the architecture whose complexity increases according to the increasing detection length.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.20-35
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.15-26
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• 2005

In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.