• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.293-297
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• 2000

Multiseeding with (100)/(100) grain junctions of top-seeded melt growth (TSMG) processed YBCO superconductors was studied. The effect of the number of seeds and the distance between two seeds on the levitation forces and the trapped magnetic fields of the TSMG-processed YBCO samples was investigated. Multiple seeding shortened the processing time for the fabrication of TSMC-processed YBCO superconductors. The large magnetic field was trapped at the grain junction when two seeds was placed without spacing, while the amount of the magnetic field decreased when the seed distance increased. This is attributed to the increased amount of the residual melt phases around the grain junctions.

• Progress in Superconductivity
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• 제8권1호
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• pp.8-15
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• 2006

The size of the superconducting domains and the critical current density inside these domains have to be enhanced for most of cryomagnetic applications of melt-textured YBCO bulks. To enlarge the size of the domains we studied the multi-seeding technique based on a well-established procedure for preparing high quality YBCO monoliths using self-made SmBCO seeds. The distance between the seeds was optimised as a result of the investigation of the effects of various seed distances on the characteristics of the grain boundary Junctions. The influences of a-b plane intersections and c-axis misalignments were researched. Thereby, a small range of tolerance of the misorientations between the seed crystals was found. Field mapping was applied to control the materials quality and the superconductor's grain structure was investigated using polarisation microscopy. YBCO function elements with iou. seeds in a line and an arrangement of making type (100)/(100) and (110)/(110) boundary junctions, respectively, were processed. The trapped field profile in both sample types shows single domain behaviour. To demonstrate the potential of the multi-seeding method a ring-shaped sample was processed by placing sixteen seeds in a way to make both (100)/(100) and (110)/(110) grain junctions at the same time. The results up to now are very promising to prepare large single domain melt-textured YBCO semi-finished products in complex shapes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.85-89
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• 1997

A microstructure of realistic ZnO varistor was constructed by Voronoi network and studied cia computer simulation. The grain size and standard deviation was calculated with new method and have good agreement with experimental data. In this network, the grain boundary conditions of three different type are randomly distributed. The three electrical boundary conditions . (1) type A junctions (high nonlinearity); (2) type B junctions (low nonlinearity); (3) type C junctions (linear with low-resistivity) are fitted from the experimental measurement. The electrical properties were studied by varying the boundary type concentration and the disorder parameter d. The shape of I-V characteristic curve of the network is affected by the type concentration and the disorder parameter has an effect on the double inflected region.

• 한국초전도ㆍ저온공학회논문지
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• 제20권3호
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• pp.5-10
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• 2018

This study presents that various grain boundary junctions are prepared by controlling the seed orientation combined with an artificial hole in a melt process REBCO bulk superconductor. Large grain YBCO superconductors have been fabricated with various grain boundary junctions that the angle between the grain boundary and the <001> axis of Y123 crystal is $0^{\circ}$, $30^{\circ}$ and $45^{\circ}$, respectively. The presence of the artificial hole is beneficial for the formation of clean grain boundary junction and single peak trapped magnetic field profiles have been obtained. Artificial hole makes two growth fronts meet at a point on a periphery of the artificial hole. The presence of artificial hole is not likely to affect on the distribution of Y211 particles. The newly formed <110> facet lines are explained by the formation of new Y123/liquid interface with (010) crystallographic plane.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2003년도 춘계학술발표회 초록집
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• pp.4-4
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• 2003

Various Cu films were fabricated using sputtering and electroplating with and without additive, and their surface damages after annealing were investigated. After annealing at 43SoC, the difference between damage morphologies of the films was observed. In some films stress-induced grooves along the grain boundaries were observed, while in the others voids at the grain boundary triple junctions were observed. It was also observed that the stress-induced groove was formed along the high energy grain boundaries. It was found out that the difference of the morphologies of surface damages in Cu films depends on not process type but grain boundary characteristics. To explain the morphological difference of surface damages, a simple parameter considering the contributions of grain structures and grain boundary characteristics to surface and grain boundary diffusions is suggested. The effective grain boundary area, which is a function of grain size, film thickness and the fraction of high energy grain boundaries, played a key role in the morphological difference.

• Interaction and multiscale mechanics
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• 제1권2호
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• pp.191-209
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• 2008

In this paper, we model grain boundary evolution based on a multiple level set method. Grain boundary migration under a curvature-induced driving force is considered and the level set method is employed to deal with the resulting topological changes of grain structures. The complexity of using a level set method for modeling grain structure evolution is due to its N-phase nature and the associated geometry compatibility constraint. We employ a multiple level set method with a predictor-multicorrectors approach to reduce the gaps in the triple junctions down to the grid resolution level. A ghost cell approach for imposing periodic boundary conditions is introduced without solving a constrained problem with a Lagrange multiplier method or a penalty method. Numerical results for both uniform and random grain structures evolution are presented and the results are compared with the solutions based on a front tracking approach (Chen and Kotta et al. 2004b).

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.99-102
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• 2000

We have studied the effects of d-wave symmetry on the critical current of YBa$_2$Cu$_3$O$_7$ step-edge Josephson junctions. The critical current along various misorientation angle was measured and analyzed with the concept of grain-boundary junctions with d-wave symmetry. Experimental results of c-oriented YBCO step-edge junctions with various in-plane misorientation angles were qualitatively in good agreement with the theory. The out-of-plane misorientation angle is usually formed between two grains with the c axes perpendicular to each other and is normally not controllable.

• E2M - 전기 전자와 첨단 소재
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• 제10권7호
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• pp.659-667
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• 1997

The influence of SiO$_2$on the microstructure and electrical properties of zinc oxide varistor was investigated. Zn$_2$SiO$_4$third phase in the sintered body was found at grain boundaries, multiple grain junctions, and occasionally within ZnO grains. This phase acted as a grain growth inhibitor, which retard the grain growth of the ZnO matrix by impeding migration on the grain boundaries. As SiO$_2$ addition increases, average grain size decreased from 40.6${\mu}{\textrm}{m}$ to 26.9${\mu}{\textrm}{m}$ due to the pinning effect by Zn$_2$SiO$_4$ and drag effect by Si segregation at grain boundaries, the breakdown voltage consequently increased. When SiO$_2$ addition is increased, interface state density decreased, however, the barrier height increased by decrease of donor concentration, as a result, the nonlinear exponent increased and leakage current decreased. While, as SiO$_2$ addition increase, it was found that the apparent dielectric loss factor shows a tendency of decrease. Wholly, electrical properties of zinc oxide varistor can be said to be improved by SiO$_2$addition.

• 한국재료학회지
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• 제9권1호
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• pp.86-91
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• 1999

(001) $\textrm{SrTiO}_3$(STO) 기판위에 고온초전도 $\textrm{YBa}_{2}\textrm{Cu}_{3}\textrm{O}_{7-x}$(YBCO)박막을 이용한 계단형 모서리 임계접합을 제조하였다. STO (100) 단결정 기판위에 계단형 모서리(step-edge)를 제작하기 위한 이온밀링 마스크로 plasma enhanced chemical vapor deposition방법으로 증착된 diamond-like carbon (DLC) 박막을 사용하였고, oxygen reactive ion etch 방법으로 건식식각하였다. 이렇게 제작된 계단형 모서리 기판위에 c-축 수직한 YBCO 박막과 STO박막을 pulsed laser deposition방법으로 에피텍셜하게 증착하였다. 계단의 상층과 하층에서 모두 임계가 형성되었으며 이 접합의 임계온도는 77 K 이상이었고 16K에서 $\textrm{I}_{c}\textrm{R}_{n}$products가 7.5mV, 77 K에서 0.3mV의 값을 나타내었다. 이들 전류-전압 특성은 two noisy resistively shunted Josephson junction 모델을 잘 만족하였다.

• 한국세라믹학회지
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• 제44권2호
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• pp.116-123
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• 2007

Electrical properties of AlN ceramics sintered with 1 wt% $Y_2O_3$ have been investigated. From the impedance spectroscopy, electrical conductivity of grain boundary was found to be much lower than that of grain. DC conductivity measurement showed the electrode polarization effects caused by blocking electrode. The heat-treatment at $1700^{\circ}C$ of the specimen sintered at $1850^{\circ}C$ transformed continuous pain boundary phases along triple boundary junctions into isolated particles in grain comers. The heat-treatment induced decreases both in grain and grain boundary conductivity, and in DC electrical conductivities. From the analysis on the transference number, ionic conductivity was shown to be more dominant than electron conductivity, which was due to ion compensation mechanism during oxygen incorporation into grain.