• Korean Journal of Materials Research
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• v.16 no.9
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• Journal of the Korean Vacuum Society
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• v.5 no.1
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• pp.39-47
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• 1996

The segregation of S in electrotransport-purified polycrystaline $\alpha$-Ti and Ti-aluminide alloys has been studied by Auger electron spectroscopy(AES), Ion scattering spectroscopy(ISS) and Secondary ion mass spectrometry(SIMS) in the temperature range extending from 20 to $1000^{\circ}C$. The chemisorbed oxygen and carbon on Ti were observed to disappear at T>$400^{\circ}C$ after which the S signal increased to levels approaching 0.5 monolayer. At lower temperatures the presence of the surface oxygen and carbon appeared to inhibit the segregation, presumably because there were no available surfaces sites for the S emerging from the bulk. The activation energy for the S segregation in pure polycrystaline Ti was determined to be 16.7 kcal/mol, which, when compared to S segretation from single-crystal Ti, is quite small and suggests grain boundary or defect diffusion segregation kinetics. In the Ti-aluminide alloys, the presence of Al appeared to enhance the retention of surface oxygen which, in turn, substantially reduced the S segretation. The $\gamma$ alloy, with its high Al content, exhibited the greatest retention of surface oxygen and the smallest quantity of the S segregation(T$\simeq1000^{\circ}C$).

• Journal of Powder Materials
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• v.31 no.2
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• pp.146-151
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• 2024

Pure SnO₂ has proven very difficult to densify. This poor densification can be useful for the fabrication of SnO₂ with a porous microstructure, which is used in electronic devices such as gas sensors. Most electronic devices based on SnO₂ have a porous microstructure, with a porosity of > 40%. In pure SnO₂, a high sintering temperature of approximately 1300℃ is required to obtain > 40% porosity. In an attempt to reduce the required sintering temperature, the present study investigated the low-temperature sinterability of a current system. With the addition of TiO₂, the compositions of the samples were Sn_1-xTi_xO₂-CoO(0.3wt%)-CuO(2wt%) in the range of x ≤ 0.04. Compared to the samples without added TiO₂, densification was shown to be improved when the samples were sintered at 950℃. The dominant mass transport mechanism appears to be grain-boundary diffusion during heat treatment at 950℃.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.174-181
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• 2003

Ta diffusion barriers have been deposited on Si (100) substrate by applying a negative substrate bias voltage. The effect of the substrate bias voltage on the properties of the Ta films was investigated. In the case of the Ta films deposited without the substrate bias voltage, a columnar structure and small grains were observed distinctly, and the electrical resistivity of the deposited Ta films was very high (250 $\mu\Omega$cm). By applying the substrate bias voltage, no clear columnar structure and grain boundary were observed. The resistivity of the Ta films decreased remarkably and at a bias voltage of -125 V, reaching a minimum value of 40 $\mu\Omega$cm, which is close to that of Ta bulk (13 $\mu\Omega$cm). The thermal stability of Cu(100 mm)/Ta(50 mm)/Si structures was evaluated after annealing in H2 atmosphere for 60 min at various temperatures. The Ta films deposited by applying the substrate bias voltage were found to be stable up to $600^{\circ}C$, while the Ta films deposited without the substrate bias voltage degraded at $400^{\circ}C$.

• Proceedings of the Korean Nuclear Society Conference
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• 1997.05b
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• pp.165-170
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• 1997

Samples of extruded dispersions of 24 vol.% spherical U-2wt%Mo and U-10wt.%Mo powders in an aluminum matrix were annealed for over 2,000 hours at 40$0^{\circ}C$. No significant dimensional changes occurred in the U-1025.%Mo/aluminum dispersions. The U-2wt.%Mo/aluminum dispersion, however, increased in volume by 26% after 2,000 hours at 40$0^{\circ}C$. This large volume change is mainly due to the formation of voids and cracks resulting from nearly complete interdiffusion of U-Mo and aluminum. Interdiffusion between U-10wt.%Mo and aluminum was found to be minimal. The different diffusion behavior is primarily due to the fact that U-2wt.%Mo decomposes from an as-atomized metastable r-phase(bcc) solid solution into the equilibrium r-U and U$_2$Mo two-phase structure during the experiment, whereas U-10wt.%Mo retains the metastable r-phase structure after the 2,000 hours anneal and thereby displays superior thermal compatibility with aluminum compared to U-2wt.%Mo. In addition, the molybdenium supersaturated in U-10wt.%Mo particles inhibits the diffusion of aluminum atoms along the grain boundary into the particle. Also, the dissolution of only a few Mo atoms in UAL$_3$ retards the formation of the intermediate phase, as Mo atoms need to migrate from new intermetallic compounds to unreacted islands.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.5 no.1
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• pp.39-52
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• 2007

Quantitative analysis on release behavior of the $^{85}Kr\;and\;^{14}C$ fission gases from the spent fuel material during the voloxidation and OREOX process has been performed. This thermal treatment step in a remote fabrication process to fabricate the dry-processed fuel from spent fuel has been used to obtain a fine powder The fractional release percent of fission gases from spent fuel materials with burn-up ranges from 27,000 MWd/tU to 65,000 MWd/tU have been evaluated by comparing the measured data with these initial inventories calculated by ORIGEN code. The release characteristics of $^{85}Kr\;and\;^{14}C$ fission gases during the voloxidation process at $500^{\circ}C$ seem to be closely linked to the degree of conversion efficiency of $UO_2\;to\;U_3O_8$ powder, and it is thus interpreted that the release from grain-boundary would be dominated during this step. The high release fraction of the fission gas from an oxidized powder during the OREOX process would be due to increase both in the gas diffusion at a temperature of $500^{\circ}C$ in a reduction step and in U atom mobility by the reduction. Therefore, it is believed that the fission gases release inventories in the OREOX step come from the inter-grain and inter-grain on $UO_2$ matrix. It is shown that the release fraction of $^{85}Kr\;and\;^{14}C$ fission gases during the voloxidation step would be increased as fuel burn-up increases, ranging from 6 to 12%, and a residual fission gas would completely be removed during the OREOX step. It seems that more effective treatment conditions for a removal of volatile fission gas are of powder formation by the oxidation in advance than the reduction of spent fuel at the higher temperature.

• Journal of the Korean Magnetics Society
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• v.12 no.2
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• pp.41-45
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• 2002

The low-field tunnel-type magnetoresistance (MR) properties of sol-gel derived $La_{0.7}Pb_{0.3}MnO_3(LPMO)$ thin film deposited on different substrate have been investigated. Polycrystalline thin films were fabricated by spin-coating on $SiO_2/Si(100)$ substrate and that with yttria-stabilized zirconia (YSZ) buffer layer, while c-axis-oriented thim film was grown on $LaAlO_3(001)$ (LAO) single crystal substrate. The full width half maximum (FWHM) of the rocking curve scan of LPMO/LAO film is $0.32^{\circ}$. Tunnel-type MR ratio is 0.52 % in $LPMO/SiO_2/Si$(100) film and that of $LPMO/YSZ/SiO_2/Si$(100) film is as high as 0.68 %, whereas that of LPMO/LAO(001) film is less than 0.4 % under the applied field of 500 Oe at 300 K. Well-pronounced MR hysteresis was registered with an MR peak in the vicinity of the coercive field. The low-field tunnel-type MR characteristics of thin films deposited on different substrates originates from the behavior of grain boundary properties.