• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1055-1061
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• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.41-43
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• 2000

멀티미디어 시스템에서는 미디어 데이터의 연속성을 보장하는 것이 중요한 문제이다. 90년대에 제안된 구역분할 디스크에서 연속성을 보장하면서 멀티미디어를 효과적으로 저장, 전송하기 위하여 새로운 스케줄링 방식과 데이터 블록의 배치가 제안되었다. 이 방식은 구역을 순환하면서 데이터 블록을 배치시키고 SCAN 알고리즘으로 데이터를 읽어 들이는 방식이다. 이 경우 SCAN 알고리즘으로 데이터를 읽어 들이므로 이중 버퍼링(double buffering) 방법을 사용하게 된다. 이중 버퍼링의 데이터를 읽어 들이는 주기와 서비스 주기의 불일치성으로 인하여 새로운 스트림의 요청이 있을 때 기존의 서비스 스트림에 주기시간의 증가로 인한 데이터의 지연문제(jitter)가 발생한다. 본 논문에서는 구역분할 디스크를 이용하는 비디오 서버에서 새로운 요구의 도착으로 인하여 발생하는 데이터 지연 문제(jitter)를 해결하기 위하여 선행 버퍼링이란 기법을 제시한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2521-2530
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• 1997

In this paepr, we present a video-on-demand (VOD) system design model that address and integrates a number of inter-related issues. Then with analysis and performance evaluation, we investigate various aspects of disk and buffer managements in the given model. Based on the analysis results, we suggest that a distributed buffering scheme with intermediate buffers may te useful to transform bursty disk accesses into a continuous stream for for glitch-free performance of VOD systems. Also, through simulation, we illustrate that massive multimedia information storage design techniques such as prefetching, clustered striping, and real-time disk scheduling integrated with the distributed buffering mechanism may enhance end-to-end real-time performance of VOD systems under wide-area networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.