• 전자공학회논문지
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• 제53권3호
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• pp.39-45
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• 2016

본 논문에서는 게르마늄 응축 공정을 모델링하고 공정을 적용한 나노와이어 구조의 게르마늄 PMOSFET의 특성을 소자 시뮬레이션을 통하여 확인하였다. 기존의 연구 결과들을 토대로 하여 모델링을 수행한 결과, 게르마늄 응축 공정 과정에서 얻게 되는 벌크 영역에서의 게르마늄 농도($C_B$)에 대한 실리콘 게르마늄-실리콘 산화막 계면에서의 게르마늄 농도의 비율($C_S$)은 약 4.03, 해당 공정 온도에서 게르마늄 원자의 유효 확산 계수($D_{eff}$)은 약 $3.16nm^2/s$으로 추출되었다. 나아가, 게르마늄 응축 공정을 통하여 구현할 수 있는 실리콘 코어 상에 얇은 게르마늄 채널을 갖는 나노와이어 채널 구조의 PMOSFET을 설계하고 성능을 분석하였다. 이를 통하여, 전영역을 실리콘으로 혹은 게르마늄으로 하는 채널을 갖는 소자에 비하여 실리콘 코어-게르마늄 채널의 동축 이종접합 채널을 갖는 소자가 우수한 특성을 가질 수 있음을 확인하였다.

• 한국전기전자재료학회논문지
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• 제29권7호
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• pp.435-439
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• 2016

We developed a Ag nanowire patterning technique using a water-soluble sacrificial layer. To form a water-soluble sacrificial layer, germanium was deposited on the substrate and then water-soluble germanium oxide was simply formed by thermal oxidation of germanium using a conventional furnace. The formation of Ag nanowire patterns with various line and space arrangements was successfully demonstrated using this patterning process. The main advantage of this patterning technique is that it does not use a strong acid etchant, thereby preventing damage to the Ag nanowire during the patterning process.

• 대한기계학회논문집B
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• 제39권10호
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• pp.825-829
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• 2015

나노선에서 코어-셸 헤테로 구조를 도입함으로써 열 전도율을 낮출 수 있으며, 이로 인해 열전 효율(ZT)을 향상시킬 수 있다는 것이 이론 연구를 통해 제안되었다. 본 논문에서는 코어-셸 나노선의 열전도율 감소를 실험적인 방법을 통해 확인하였다. 화학증기 증착법을 통해 만든 게르마늄-규소 $_x$ 게르마늄 $_{1-x}(Ge-Si_xGe_{1-x})$ 코어-셸 나노선의 열전도율을 마이크로 크기의 뜬 디바이스를 이용하여 측정하였다. 셸에서 측정된 실리콘의 함유율(x)는 0.65 로 확인하였으며, 게르마늄은 코어와 셸 사이에서, 격자 불일치(lattice mismatch)에서 비롯된 결점(defect)와 같은 역할을 한다. 또한, 4-point I-V 측정실험에, 휘트스톤 브릿지 실험을 추가 진행함으로써 측정 민감도를 강화하였다. 측정된 열전도율은 상온에서 9~13 W/mK 으로써, 비슷한 지름을 가지는 게르마늄 나노선과 비교하였을 때, 열전도율이 약 30 % 낮아졌음을 확인하였다.

• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.288-288
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• 2013

Lithium-ion battery (LIB) is one of the most important rechargeable battery and portable energy storage for the electric digital devices. In particular, study about the higher energy capacity and longer cycle life is intensively studied because of applications in mobile electronics and electric vehicles. Generally, the LIB's capacity can be improved by replacing anode materials with high capacitance. The graphite, common anode materials, has a good cyclability but shows limitations of capacity (~374 mAh/g). On the contrary, silicon (Si) and germanium(Ge), which is same group elements, are promising candidate for high-performance LIB electrodes because it has a higher theoretical specific capacity. (Si:4200 mAh/g, Ge:1600 mAh/g) However, it is well known that Si volume change by 400% upon full lithiation (lithium insertion into Si), which result in a mechanical pulverization and poor capacity retention during cycling. Therefore, variety of nanostructure group IV elements, including nanoparticles, nanowires, and hollow nanospheres, can be promising solution about the critical issues associated with the large volume change. However, the fundamental research about correlation between the composition and structure for LIB anode is not studied yet. Herein, we successfully synthesized various structure of nanowire such as Si-Ge, Ge-Carbon and Si-graphene core-shell types and analyzed the properties of LIB. Nanowires (NWs) were grown on stainless steel substrates using Au catalyst via VLS (Vapor Liquid Solid) mechanism. And, core-shell NWs were grown by VS (Vapor-Solid) process on the surface of NWs. In order to characterize it, we used FE-SEM, HR-TEM, and Raman spectroscopy. We measured battery property of various nanostructures for checking the capacity and cyclability by cell-tester.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.376-376
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• 2012

Semiconductor nanowires (NWs) are future building block for nano-scale devices. Especially, Ge NWs are fascinated material due to the high electrical conductivity with high carrier mobility. It is strong candidate material for post-CMOS technology. However, thermal stability of Ge NWs are poor than conventional semiconductor material such as Si. Especially, when it reduced size as small as nano-scale it will be melted around CMOS process temperature due to the melting point depression. Recently, Graphene have been intensively interested since it has high carrier mobility with single atomic thickness. In addition, it is chemically very stable due to the $sp^2$ hybridization. Graphene films shows good protecting layer for oxidation resistance and corrosion resistance of metal surface using its chemical properties. Recently, we successfully demonstrated CVD growth of monolayer graphene using Ge catalyst. Using our growth method, we synthesized Ge/graphene core/shell (Ge@G) NW and conducted it for highly thermal stability required devices. We confirm the existence of graphene shell and morphology of NWs using SEM, TEM and Raman spectra. SEM and TEM images clearly show very thin graphene shell. We annealed NWs in vacuum at high temperature. Our results indicated that surface melting phenomena of Ge NWs due to the high surface energy from curvature of NWs start around $550^{\circ}C$ which is $270^{\circ}C$ lower than bulk melting point. When we increases annealing temperature, tip of Ge NWs start to make sphere shape in order to reduce its surface energy. On the contrary, Ge@G NWs prevent surface melting of Ge NWs and no Ge spheres generated. Furthermore, we fabricated filed emission devices using pure Ge NWs and Ge@G NWs. Compare with pure Ge NWs, graphene protected Ge NWs show enhancement of reliability. This growth approach serves a thermal stability enhancement of semiconductor NWs.