• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.39-45
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• 2016

In this paper, prcess modeling of germanium condensation has been performed and a germanium PMOSFET having nanowire channel implented by the condensation process has been designed and characterized by device simulations. Based on the previous experimental results, our modeling results demonstrate that the ratio of germanium concentration at the silicon germanium-silicon dioxide interface ($C_S$) to that in the bulk region ($C_B$) which are obtainable during the germanium condensation is approximately 4.03 and the effective diffusion coefficient ($D_{eff}$) of germanium atom is $3.16nm^2/s$. Furthermore, a germanium nanowire-channel PMOSFET having the ultra-thin germanium channel on the silicon core that can be fabricated by the germanium condensation has been designed and characterized. As the result, it is confirmed that the proposed device having the coaxial nanowire consisting of silicon core and germanium channel might have superior performances over the device with either all-silicon or all-germanium channel.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.435-439
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• 2016

We developed a Ag nanowire patterning technique using a water-soluble sacrificial layer. To form a water-soluble sacrificial layer, germanium was deposited on the substrate and then water-soluble germanium oxide was simply formed by thermal oxidation of germanium using a conventional furnace. The formation of Ag nanowire patterns with various line and space arrangements was successfully demonstrated using this patterning process. The main advantage of this patterning technique is that it does not use a strong acid etchant, thereby preventing damage to the Ag nanowire during the patterning process.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.39 no.10
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• pp.825-829
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• 2015

Theoretical calculations suggest that the thermoelectric figure of merit (ZT) can be improved by introducing a core-shell heterostructure to a semiconductor nanowire because of the reduced thermal conductivity of the nanowire. To experimentally verify the decrease in thermal conductivity in core-shell nanowires, the thermal conductivity of Ge-SixGe1-x core-shell nanowires grown by chemical vapor deposition (CVD) was measured using suspended microdevices. The silicon composition (Xsi) in the shells was measured to be about 0.65, and the remainder of the germanium in the shells was shown to play a role in decreasing defects originating from the lattice mismatch between the cores and shells. In addition to the standard four-point current- voltage (I-V) measurement, the measurement configuration based on the Wheatstone bridge was attempted to enhance the measurement sensitivity. The measured thermal conductivity values are in the range of 9-13 W/mK at room temperature and are lower by approximately 30 than that of a germanium nanowire with a comparable diameter.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.288-288
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• 2013

Lithium-ion battery (LIB) is one of the most important rechargeable battery and portable energy storage for the electric digital devices. In particular, study about the higher energy capacity and longer cycle life is intensively studied because of applications in mobile electronics and electric vehicles. Generally, the LIB's capacity can be improved by replacing anode materials with high capacitance. The graphite, common anode materials, has a good cyclability but shows limitations of capacity (~374 mAh/g). On the contrary, silicon (Si) and germanium(Ge), which is same group elements, are promising candidate for high-performance LIB electrodes because it has a higher theoretical specific capacity. (Si:4200 mAh/g, Ge:1600 mAh/g) However, it is well known that Si volume change by 400% upon full lithiation (lithium insertion into Si), which result in a mechanical pulverization and poor capacity retention during cycling. Therefore, variety of nanostructure group IV elements, including nanoparticles, nanowires, and hollow nanospheres, can be promising solution about the critical issues associated with the large volume change. However, the fundamental research about correlation between the composition and structure for LIB anode is not studied yet. Herein, we successfully synthesized various structure of nanowire such as Si-Ge, Ge-Carbon and Si-graphene core-shell types and analyzed the properties of LIB. Nanowires (NWs) were grown on stainless steel substrates using Au catalyst via VLS (Vapor Liquid Solid) mechanism. And, core-shell NWs were grown by VS (Vapor-Solid) process on the surface of NWs. In order to characterize it, we used FE-SEM, HR-TEM, and Raman spectroscopy. We measured battery property of various nanostructures for checking the capacity and cyclability by cell-tester.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.376-376
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• 2012

Semiconductor nanowires (NWs) are future building block for nano-scale devices. Especially, Ge NWs are fascinated material due to the high electrical conductivity with high carrier mobility. It is strong candidate material for post-CMOS technology. However, thermal stability of Ge NWs are poor than conventional semiconductor material such as Si. Especially, when it reduced size as small as nano-scale it will be melted around CMOS process temperature due to the melting point depression. Recently, Graphene have been intensively interested since it has high carrier mobility with single atomic thickness. In addition, it is chemically very stable due to the $sp^2$ hybridization. Graphene films shows good protecting layer for oxidation resistance and corrosion resistance of metal surface using its chemical properties. Recently, we successfully demonstrated CVD growth of monolayer graphene using Ge catalyst. Using our growth method, we synthesized Ge/graphene core/shell (Ge@G) NW and conducted it for highly thermal stability required devices. We confirm the existence of graphene shell and morphology of NWs using SEM, TEM and Raman spectra. SEM and TEM images clearly show very thin graphene shell. We annealed NWs in vacuum at high temperature. Our results indicated that surface melting phenomena of Ge NWs due to the high surface energy from curvature of NWs start around $550^{\circ}C$ which is $270^{\circ}C$ lower than bulk melting point. When we increases annealing temperature, tip of Ge NWs start to make sphere shape in order to reduce its surface energy. On the contrary, Ge@G NWs prevent surface melting of Ge NWs and no Ge spheres generated. Furthermore, we fabricated filed emission devices using pure Ge NWs and Ge@G NWs. Compare with pure Ge NWs, graphene protected Ge NWs show enhancement of reliability. This growth approach serves a thermal stability enhancement of semiconductor NWs.