• 센서학회지
• /
• 제29권1호
• /
• pp.68-73
• /
• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• 한국조경학회지
• /
• 제41권2호
• /
• pp.47-58
• /
• 2013

본 연구의 목적은 국내 노천카페의 유형을 분류하고, 평가기준을 선정하여 유형별로 평가함으로써 추후 노천카페 가이드라인을 만들 때 기초자료를 제공하는 것이다. 이를 위해 가로와의 관계성 관점에서 노천카페의 유형을 분류하기 위하여 가로변 노천카페의 전수조사가 시행되었다. 그리고 평가기준을 선정하기 위하여 문헌 조사와 중요도 조사가 사용되었고, 데이터의 분석에는 기술통계분석, 요인분석 등과 같은 통계방법들이 사용되었다. 그 결과, 노천카페의 유형은 가로와의 관계성 관점에서 가로돌출형, 가로개폐형, 혼합입체형, 가로앙각형, 사인제공형 등 5개 유형으로 분류되었다. 평가항목의 5개 요인은 접근성, 심미성, 정체성, 환경성, 문화성이었는데, 이 5개 요인의 누적기여율은 68.731%로 높은 편이었다. 이러한 평가항목을 토대로 조경 전문가 4인이 5점 리커트 방식으로 평가를 실시하였다. 유형별 평가 결과, 가로돌출형과 가로개폐형은 '심미성'과 '문화성'의 평가점수가 가장 낮았고, 혼합입체형은 '문화성'의 평가점수가 가장 낮았으며, 가로앙각형은 '접근성', '심미성', '문화성', 사인제공형은 '접근성', '정체성', '환경성'의 점수가 낮았다. 지표별 평가 결과, '문화성'의 평가점수가 가장 낮았고, 항목별 평가 결과, '장애인의 안전성', '프로그램의 흥미성', '출입의 개방성'의 평가점수가 가장 낮았다. 본 연구는 국내에서 요구와 관심은 높지만 연구가 미흡한 분야인 노천카페의 유형을 분류하고, 유형별 평가를 수행하여 정책적 시사점을 제공하였다는 것에 의의가 있다. 그러나 소로변의 노천카페만 대상으로 하였으므로 추후 주변 환경의 차이에 대한 고찰을 위하여 다양한 환경의 노천카페를 대상으로 해야 할 것이다. 또한 전문가가 평가를 시행하였으므로 추후 이용자 입장에서의 중요도와 만족도 조사도 시행되어야 할 것이다.

• 한국소성가공학회:학술대회논문집
• /
• 한국소성가공학회 2008년도 추계학술대회 논문집
• /
• pp.354-357
• /
• 2008

In this study, the casting process using forged insert was applied to manufacturing a knuckle, in order to prove that application of casting process using forged insert is likely to get the effect of light weight and superior mechanical characteristic compared with existing casting products. Firstly, in the forging experiment, it was confirmed that the optimal configuration of the forged insert could be predicted by FE analysis. And by using FVM (Finite Volume Method) software, it was verified that a proposed casting design was available. To identify the mechanical characteristic of the final casting product, the microstructual observation and hardness test were performed at the boundary zone between forging and casting part.

• 연구논문집
• /
• 통권29호
• /
• pp.173-183
• /
• 1999

The vacuum investment casting process for a large gas turbine component, Inner Preswirl Support (IPS), was simulated by using commercial FEM package ProCAST(TM) with view factor radiation method. The solid fraction in mushy zone was directly measured by Differential thermal analysis(DTA-DSC mode). Three types gating design. considering liquid flow and heat release through it. were proposed. Solidification had begun at the ribs or thin sections of the IPS casting and advanced further through the upper and lower gates. The computed temperature gradient G and G/R values at 70% solidified temperature were used for prediction of microshrinkage formation during casting. The effect of mold preheat on the thermal history of the casting displayed minute effect on the microshrinkage formation.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.607-608
• /
• 2008

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.

• 한국주조공학회지
• /
• 제13권5호
• /
• pp.424-431
• /
• 1993

A Numerical technique has been developed for the coupled heat transfer and fluid flow calculation during the casting process. In this method the SMAC technique was coupled with the concept of Volume of Fluid(VOF) to calculate melt free surface and velocity profiles within the melt, and the Energy Marker method coupled with the finite difference method was proposed for the convective and conductive heat transfer analysis in the casting. When comparing numerical calculations with experimental observations, a close correlation was evident. It has been shown that this technique is useful for proper gating and casting design, especially for thin-walled castings.

• 한국주조공학회지
• /
• 제12권5호
• /
• pp.378-389
• /
• 1992

A numerical model based on the SOLA-VOF method, which can calculate the transient free-surface configuration of the melt, has been developed in order to analyze melt flow in the investment mold. The computational results were compared with experimental results obtained from pure aluminum investment casting. Heat transfer analysis, with and without consideration of melt flow effect has been performed. It can be concluded that analysis of melt flow in the investment mold, provides the optimum conditions for gating design. It also enables more precise solidification simulation, since heat loss, while filling the thin and complex investment mold, plays an important role in determining the solidification sequence.

• 한국산업정보학회논문지
• /
• 제19권4호
• /
• pp.33-39
• /
• 2014

본 논문에서는 나노미티 기술에서 HCI와 BTI와 같은 노화 현상에 의해 야기되는 MOSFET 디지털 회로의 실패를 정확히 예측을 위한 플립플롭 기반의 온-칩 노화 센싱 회로를 제안한다. 제안된 센싱 회로는 순차회로의 가드밴드 (guardband) 위반에 대한 경고를 나타내는 타이밍 윈도우를 이용해서 노화에 의한 회로의 동작 실패 전에 경고 비트를 발생한다. 발생된 비트는 고신뢰의 시스템 설계를 위한 적응형 셀프-튜닝 방법에서 제어 신호로 사용될 것이다. 노화 센싱 회로는 0.11um CMOS 기술을 사용해서 구현되었고, 파워-게이팅 구조를 가지는 $4{\times}4$ 곱셈기에 의해서 평가되었다.

• International Journal of Naval Architecture and Ocean Engineering
• /
• 제11권1호
• /
• pp.462-473
• /
• 2019

The effects of the location and dimension of the gate, location, and volume of the feeder, application of a chill, chill volume, and heating method of the feeder with respect to the effect of the mold-designing technologies on the defect status of the products are described. It is possible to increase the solidification time of the feeder by heating feeder. Furthermore, the pressure generated from the feeder is imposed on a product, and this decreases the generation of shrinkage porosities. In this study, two types of gating and feeding systems had been proposed: the bottom L-type junctions and the top L-type junctions. Additionally, solidification behaviors, such as solidification time, shrinkage porosities, weight percentage of chill system to product, hot spot, and solidification time ratio (=Solidification time of feeder/solidification time of product), are extensively analyzed by using commercial casting simulation software. Based on the solidification behaviors, reasonable mold design, feeding system, critical feeder heating temperature, and solidification time ratios are proposed in the sand casting process for the fabrication of carrier housing in order to reduce the casting defects and to increase the recovery rate.

• 센서학회지
• /
• 제27권1호
• /
• pp.59-63
• /
• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.