• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 한국전기전자재료학회논문지
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• 제20권10호
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• pp.859-863
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• 2007

Aluminum oxide films were deposited on n-type 6H-SiC(0001) substrates by RF magnetron sputtering technique for MIS devices applications. Well-behaved C-V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $4.6{\times}10^{10}/cm^2\;eV$ in the upper half of the bandgap. The gate leakage current densities of the MIS structures were about $10^{-8}A/cm^2$ and about $10^{-6}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for a ${\pm}1\;MV/cm$, respectively These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.329-334
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• 2008

Aluminum oxide films were deposited on n-type GaN substrates by RF magnetron sputtering technique for MIS devices applications using optimized conditions, Well-behaved C - V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $9\times10^{10}/cm^2$ eV in the upper bandgap. The gate leakage current densities of the MIS structures were about $10^{-9}A/cm^2$ and about $10^{-4}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for $a{\pm}1MV/cm$, respectively. These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.54-57
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• 2003

[ $HfO_xN_y$ ] films using a hafnium tertiary-butoxide $(Hf[OC(CH_3)_3]_4)$ in plasma and $N_2$ ambient were prepared to improve the thermal stability of hafnium-based gate dielectrics. A 10% nitrogen incorporation into $HfO_2$ films showed a smooth surface morphology and a crystallization temperature as high as $200^{\circ}C$ compared with pure $HfO_2$ films. The $TaN/HfO_xN_y/Si$ capacitors showed a stable capacitance-voltage characteristics even at post-metal annealing temperature of $1000^{\circ}C$ in $N_2$ ambient and a constant value of 1.6 nm EOT (equivalent oxide thickness) irrespective of an increase of PDA and PMA temperature. Leakage current densities of $HfO_xN_y$ capacitors annealed at PDA temperature of 800 and $900^{\circ}C$, respectively were approximately one order of magnitude lower than that of $HfO_2$ capacitors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.145-145
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• 2008

High-k materials have been paid much more attention for their characteristics with high permittivity to reduce the leakage current through the scaled gate oxide. Among the high-k materials, $ZrO_2$ is one of the most attractive ones combing such favorable properties as a high dielectric constant (k= 20 ~ 25), wide band gap (5 ~ 7 eV) as well as a close thermal expansion coefficient with Si that results in good thermal stability of the $ZrO_2$/Si structure. During the etching process, plasma etching has been widely used to define fine-line patterns, selectively remove materials over topography, planarize surfaces, and trip photoresist. About the high-k materials etching, the relation between the etch characteristics of high-k dielectric materials and plasma properties is required to be studied more to match standard processing procedure with low damaged removal process. Among several etching techniques, we chose the inductively coupled plasma (ICP) for high-density plasma, easy control of ion energy and flux, low ownership and simple structure. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. During the etching process, the wafer surface temperature is an important parameter, until now, there is less study on temperature parameter. In this study, the etch mechanism of $ZrO_2$ thin film was investigated in function of $Cl_2$ addition to $BCl_3$/Ar gas mixture ratio, RF power and DC-bias power based on substrate temperature increased from $10^{\circ}C$ to $80^{\circ}C$. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by scanning emission spectroscope (SEM). The chemical state of film was investigated using energy dispersive X-ray (EDX).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.