• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.11
• /
• pp.21-30
• /
• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Proceedings of the IEEK Conference
• /
• 2003.07c
• /
• pp.2617-2620
• /
• 2003

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2$\^$m/) and the flow chart representing the proposed algorithm has been proposed. And also, we get the degree from the value of xm＋k formation to the value of k = 7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k = 7, one AND gate and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gates and sever Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.

• Proceedings of the KIPE Conference
• /
• 2016.07a
• /
• pp.393-394
• /
• 2016

A single-phase ac voltage controller controls the magnitude of ac voltage by regulating the delay angle of the input ac voltage. In this paper, the SCR gate signal generation is digitalized by using AVR, and the delay angle control technique is proposed in order to generate a balanced ac output voltage under unbalanced ac input voltage conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1995.05a
• /
• pp.86-89
• /
• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.779-782
• /
• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.9-12
• /
• 2008

For the large-sized and post-ultra definition TFT-LCD, improved drivability is prerequisite not only for the integration of driving circuit on glass but also for the chargeability of each pixel. In order to meet required drivability, currently adopted process architecture and materials are modified for the RC delay reduction, including the drastic increase of gate bus thickness and its related solution for step coverage. We present new process architecture and material selection for the next generation TFT-LCD devices.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.8
• /
• pp.33-41
• /
• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• ETRI Journal
• /
• v.34 no.2
• /
• pp.284-287
• /
• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• Proceedings of the IEEK Conference
• /
• 2007.07a
• /
• pp.223-224
• /
• 2007

To develop nuclear measurement system with characteristics including both re-configuration and multi-functions, we proposed a field programmable gate array (FPGA) technique to implement TDC which is more suitable for high energy Physics system. In TDC scheme, the timing resolution is more important than the count rates of channel. In order to manage pico-second resolution TDC, we used the delay components of FPGA, utilized the place and route (P&R) delay difference, and then got two ring oscillators. By setting P&R area constraints, we generated two precise ring oscillators with slightly different frequencies. Finally, we evaluated that the period difference of these two ring oscillators was about 60 pico-seconds, timing resolution of TDC.

• Journal of Sensor Science and Technology
• /
• v.33 no.3
• /
• pp.134-138
• /
• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.