• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.137-143
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• 2015

A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

• 한국ITS학회:학술대회논문집
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• v.2006 no.10
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• pp.179-181
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• 2006

톨게이트에서 사용되는 UHF RFID 비발디 배열 안테나를 설계하였다. 안테나의 주파수 대역은 미국 기준의 RFID UHF 대역으로 $902{\sim}928MHz$이다. 안테나 설계는 먼저 단일소자 비발디 안테나를 설계한 후, 전력분배 비율 0.3:1:1:0.3으로 $1{\times}4$ 배열한 안테나로 설계하였다. 설계된 배열 안테나는 VSWR 2:1이하에서 $850{\sim}942MHz$인 S11 특성을 보였다. 이득은 최대방사 9.93dBi를 얻었다. 안테나 제작은 주파수를 높여 scale down하여, 1소자 비발디를 제작하고 이의 특성을 측정하였다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.3
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• pp.59-65
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• 2013

This paper presents a novel calibration method for a base station system adopting an antenna array. The proposed technique utilizes Zadoff-Chu sequence, which is included in the LTE pilot signal periodically, in order to compute the phase characteristic of each antenna channel. As the Zadoff-Chu sequence exhibits an excellent autocorrelation characteristic, it is possible for the receiving base station to retrieve the Zadoff-Chu sequence transmitted from each mobile terminal. In addition, we can obtain the phase characteristic of each antenna channel, which is the ultimate goal of the calibration procedure. The proposed calibration algorithm has been implemented using an FPGA (Field Programmable Gate Array). We have applied the proposed algorithm to an array consisting of 2 antenna elements for simplicity. the phase value implied to the first and second antenna path is very accurately calculated from the proposed procedure. From the experimental test, the proposed method provides accurate calibration results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of the Korean Vacuum Society
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• v.7 no.2
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• pp.88-93
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• 1998

The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.689-692
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• 2005

In this paper, we have developed a retrodirective active array operating in the 2 GHz LS band. The retrodirective array has the property of re-directing any electromagnetic wave back to the incoming direction without any priory informations. The system is consisted of frequency mixers and antenna array. The mixer is acting as a phase conjugator. In this research, 2-port gate mixers using pHEMT and 1${\times}$4 monopole array have been used. The retrodirective array developed in this research can be applied in the base station facilities for the wireless mobile communications and RFID transponders.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.69.3-69.3
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• 2012

A high-performance low-voltage graphene field-effect transistor (FED array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 and 91 $cm^2/Vs$, respectively, at a drain bias of - I V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

• Journal of the Korean Vacuum Society
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• v.2 no.3
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• pp.331-334
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• 1993

여러 종류의 수직 또는 수평 형태의 field emitter array가 연구되었다. 그 중 수평형의 FEA는 emitter가 동일 평면 위에 구성되어 있고, gate는 고주파의 응용을 위하여서는 더욱 적합하다. 이 빗살 모양의 FEA의 구조, emission 성질, 응용에 대하여 설명한다.