• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.613-616
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• 1999

An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.103-108
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• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• Proceedings of the Korea Society for Simulation Conference
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• 1997.04a
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• pp.36-38
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• 1997

본 논문은 gate-level timed circuits의 자동 합성과 검증에 대한 것으로, 동기 회 로는 디자인을 최적화하기 위해 합성 절차가 사용된 동안 설계서에 명시된 시간 정보에 속 한 비동기 회로의 일부로서 이 시스템은 열거된 일반적인 회로 작용과 시간의 요구 조건에 대해 설계를 해석한다. 이 설계는 영향을 미치는 상태 공간을 구하기 위해 정확하고 효과적 인 시간 해석 알고리즘을 사용해 해석할 수 있는 그래픽 표현으로 자동적으로 변환된다. 이 상태공간으로부터 합성 절차는 standard-cells과 gate-arrays와 같은 반 주문형 반도체로 매핑을 용이하게 하기 위해 기본 게이트만을 사용해 어려움을 해결하는 시간에 대한 회로 유도된다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.171-175
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• 1996

Gate insulator for Si field emitter is usually formed by e-beam evaporation. However, the evaported oxide requires densification for a stable process and a reduction of gate leakage which results from its Si-rich and nonstoicheiometric structure. In this study, we have developed the process technology able to densify the evaporated oxide in H$_{2}$O ambient. Using this process, we have fabricted thefield emitter array with 625 emitters per pixel, of which gate hole diameter is 1.4.mu.m, for the pixel, anode current of 14.3.mu.A was extracted at a gate bias of 100V and gate leakage was about 0.27% of the total emission current.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1530-1533
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• 2005

We investigated under-gate type carbon nanotube field emitter arrays (FEAs) for back light unit (BLU) in liquid crystal display (LCD). Gate oxide was formed by wet etching of ITO coated glass substrate instead of depositing $SiO_2$ on the glass substrate. Wet etching is easer and simpler than depositing and etching of thick gate oxide to isolate the gate metal from cathode electrode in triode. Field emission characteristic s of triode structure were measured. The maximum current density of 92.5 ${\mu}A/cm^2$ was when the gate and anode voltage was 95 and 2500 V, respectively at the anode-cathode spacing of 1500 ${\mu}m$.

• Journal of Korean Electronics
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• v.3 no.7
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• pp.125-132
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• 1983

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.59-65
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• 1999

In this paper, we design a entorpy encoder of HDTV/DTV encoder blocks on the basis of MPEG-II. The designed entropy encoder outputs its bit stream at 9Mbps bit rate inserting zero-stepping block to protect the depletion of buffer in case that the generated bit stream is stored in buffer and uses not only PROM bit combinational circuit to solve the problem of critical path, and packer block, one of submerge, is designed to packing into 24 bit unit using barrel shifter, and it is constructed to blocks of header information encoder, input information delay, submerge, and buffer control. Designed circuits is verified by VHDL function simulation, as a result of performing P&R with Gate compiler that apply $0.8{\mu}m$ Gate Array specification, pin and gate number of total circuits has been tested to each 235 and about 120,000.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.783-789
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• 2002

In this paper, V-band MMIC coupled oscillator arrays are presented. In the proposed array, two push-pull patch antennas are synchronized by using strong electromagnetic coupling between two antennas. As a result, total size of the array is reduced and the array can be integrated in a single chip. To verify proposed array concept, two 1$\times$2 arrays are designed and fabricated using standard 0.15 um gate length pHEMT MMIC process. The circuits are mounted in an oversized waveguide and measured. The first array shows 0.5 dBm at 56.372 GHz and the second one has an output of 5.85 dBm at 60.147 GHz.