• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1089-1094
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• 2013

In this study, we propose how th implement a MDDI(Mobile Display Digital Interface) protocol packet generation method in software. MDDI protocol is widely used in mobile display device. MDDI protocol packets are generated by software within micro processor. This method needs the minimum hardware configuration. In order to implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor are converted into LVDS signals, and transmitted by hardware within FPGA. This study suggests the benefits of the way how software can easily create a variety of packet. But, this proposed method takes more time in packet transmission compared to the traditional method. This weakness remains as a future challenge, which can be soon improved.

• Journal of radiological science and technology
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• v.36 no.2
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• pp.157-163
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• 2013

Multileaf collimators whose Pb leaves are moving in two-dimensional directions have been used. We propose a different concept three-dimensional (3D) collimator with 3D shape that is automatically changeable to modulate the radiation dose even for complex tumors in real time. A voxel collimator, including a hinged Pb plane and a 3D assembly of many voxel collimators, was used. In each frame rotation axis, a motor, which was controlled by a circuit with field-programmable gate array (FPGA) board connected with computer, was operated according to a predetermined plan. Simulations of that, which are generally used for planning, were performed and compared with experimental results.

• Nuclear Engineering and Technology
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• v.50 no.6
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• pp.860-868
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• 2018

This article presents a new design of earthquake instrumentation that is suitable for quick decision-making after the seismic event at the nuclear power plant (NPP). The main objective of this work is to ensure more availability of the NPP by expediting walk-down period when the seismic wave is incident. In general, the decision-making to restart the NPP after the seismic event requires more than 1 month if an earthquake exceeds operating basis earthquake level. It affects to the plant availability significantly. Unnecessary shutdown can be skipped through quick assessments of operating basis earthquake, safe shutdown earthquake events, and damage status to structure, system, and components. Multidecision parameters such as cumulative absolute velocity, peak ground acceleration, Modified Mercalli Intensity Scale, floor response spectrum, and cumulative fatigue are discussed. The implementation scope on the field-programmable gate array platform of this work is limited to cumulative absolute velocity, peak ground acceleration, and Modified Mercalli Intensity. It can ensure better availability of the plant through integrated decision-making process by automatic assessment of NPP structure, system, and components.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.100-104
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• 2005

The injection molding is very effective process for various plastic products due to its high productivity. It is also good fur precise products like optical parts. Various thermoplastic materials are also available with this injection molding process. In recent, however, as the overall size of the product increases and micro or nano scale of patterns are applied to the products, we now have some problems such as low fidelity of the replication of the pattern, high molding pressure, or warpage from the in-mold stress. Injection/compression molding is studied to overcome those problems in molding large thin plate with micro pattern array on its surface. An injection compression mold is designed to 3 pieces mold for side gate. We install 4 pressure transducers and 9 thermocouples to measure the melt pressure and surface temperature in the cavity during the process. As a result, the maximum molding pressure for injection compression molding is reduced to 1/3 compared to injection molding and the uniformity of the pressure in the cavity is enhanced by about 15%.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.285-290
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• 2020

This paper presents a time synchronization algorithm based on PLL for application to telemetry systems and implement FPGA logic. The large aircraft of the telemetry system acquires status information through each distributed acquisition devices and analyzes the flight status in real time. For this reason, time synchronization between systems is important to improve precision. This paper presents a PLL based time synchronization algorithm that is less complex than other time synchronization methods and takes less time to process data because there is minimized message transmission for synchronization. The validity of proposed algorithm is proved by simulation of Python. And the VHDL logic was implemented in FPGA to check the time synchronization performance.

• Proceedings of the KIEE Conference
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• summer
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• pp.325-326
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• 2004

전력선통신(PLC: Power Line Communication)은 기존의 전기선을 이용하여 별도의 전용선 설치 없이 통신이 가능한 기술로서 효율적인 PLC 통신을 위해서는 가장 기본적인 기저대역의 송, 수신부상 의 원활한 데이터 전송이 이루어져야 한다. 본 논문에서는 확산대역방식의 PLC통신시스템의 수신부의 핵심모듈인 정합필터를 HDL(hardware description language)을 이용한 디지털 하드웨어인 에 위한 디지털 하드웨어인 FPGA(Field Programmable Gate Array)클 이용하여 구현하였다. 즉, 본 논문에서는 BPSK(Binary Phase Shift Keying) 변조 및 256칩 확산코드를 이용한 확산변조파형에 대한 디지털 정합필터를 FPGA로 구현하고 상관특성을 확인함으로서 모의실험상의 파형과 구현된 하드웨어상의 상관파형이 일치함을 확인하였다.

• Nuclear Engineering and Technology
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• v.45 no.4
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• pp.477-488
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• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.54 no.5
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• pp.798-807
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• 2021

The directivity characteristics of acoustic transducers for conventional single-beam echo sounders considerably limit the detection of fish-size information in acoustic field surveys. To overcome this limitation, using the split-aperture technique to estimate the direction of arrival of single-echo signals from individual fish distributed within the sound beam represents the most reliable method for fish-size classification. For this purpose, we design and develop a split-beam data acquisition and processing system to obtain fish-size information in conjunction with a 50-kHz single-beam echo sounder. This split-beam data acquisition and processing system consists of a notebook PC, a field-programmable gate array board, an external single-transmitter module with a matching network, and four-channel receiver modules operating at a frequency of 50-kHz. The functionality of the developed split-beam data processor is tested and evaluated. Acoustic measurements in an experimental water tank showed that the developed data acquisition and processing system can be used as a fish-sizing echo sounder to estimate the size distribution of individual fish, although an external single-transmitter module with a matching network is required.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.41-48
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• 2018

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.