• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Journal of Power Electronics
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• v.14 no.5
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

• Journal of Power Electronics
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• v.13 no.1
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• pp.104-112
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• 2013

This paper presents a comparative evaluation of various topologies for three-phase power converters using the hardware-in-the-loop (HIL) simulation technique. Various switch-mode AC-DC power converters are studied, and their performance with respect to total harmonic distortion (THD), efficiency, power factor and losses are analyzed. The HIL-simulation is implemented in an Altera Cyclone II DE2 Field Programmable Gate Array (FPGA) Board and in the Matlab/Simulink environment. A comparison of the simulation and HIL-simulation results is also provided.

• Advances in robotics research
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• v.2 no.1
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• pp.99-112
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• 2018

The main contribution of this work is the design of a field programmable gate array (FPGA) based ARX-Laguerre proportional-integral observation (PIO) system for fault detection and identification (FDI) in a multi-input, multi-output (MIMO) nonlinear uncertain dynamical robot manipulators. An ARX-Laguerre method was used in this study to dynamic modeling the robot manipulator in the presence of uncertainty and disturbance. To address the challenges of robustness, fault detection, isolation, and estimation the proposed FPGA-based PI observer was applied to the ARX-Laguerre robot model. The effectiveness and accuracy of FPGA based ARX-Laguerre PIO was tested by first three degrees of the freedom PUMA robot manipulator, yielding 6.3%, 10.73%, and 4.23%, average performance improvement for three types of faults (e.g., actuator fault, sensor faults, and composite fault), respectively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.9
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.223-224
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• 2007

To develop nuclear measurement system with characteristics including both re-configuration and multi-functions, we proposed a field programmable gate array (FPGA) technique to implement TDC which is more suitable for high energy Physics system. In TDC scheme, the timing resolution is more important than the count rates of channel. In order to manage pico-second resolution TDC, we used the delay components of FPGA, utilized the place and route (P&R) delay difference, and then got two ring oscillators. By setting P&R area constraints, we generated two precise ring oscillators with slightly different frequencies. Finally, we evaluated that the period difference of these two ring oscillators was about 60 pico-seconds, timing resolution of TDC.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.5
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• pp.179-184
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• 2006

In a power system, an out-of-step condition causes a variety of risk such as serious damage to system elements, tripping of loads and generators, mal-operation of relays, etc. Therefore, it is very important to detect the out-of- step condition and take a proper measure. This paper presents a study on implementation of out-of-step detection algorithm using VHDL(Very high speed Hardware Description Language). The structure of out-of-step detection algorithm is analyzed for development of out-of-step detection relay on the FPGA(Field Programmable Gate Array). The out-of-step algorithm is separated to 4 parts: DFT IP, complex power calculation IP, out-of-step detection IP, control unit. Each parts are developed and simulated by using VHDL.

• Journal of information and communication convergence engineering
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• v.11 no.3
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• pp.190-198
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• 2013

Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.223-225
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• 2007

본 논문에서는 FPGA(Field Programmable Gate Array) 기반의 전류 제어기를 설계하고 구현하였다. 기존의 DSP (Digital Signal Processor) 기반의 전류 제어기는 알고리즘 연산으로 인해 일반적으로 한 샘플링의 디지털 시지연이 발생한다. 반면에, FPGA 기반의 전류제어기는 FPGA의 높은 연산 능력을 이용하여, 알고리즘 연산에 필요한 시간을 감소시킬 수 있다. 이는 시지연이 물리적으로 줄기 때문에, 어떠한 시지연 보상 알고리즘 없이 전류 제어기의 대역폭을 향상시킬 수 있다. 구현된 FPGA 기반의 전류 제어기의 성능은 실험을 통해 검증되었다.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.242-243
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• 2017

기존 Digital Signal Processor (DSP)를 사용하여 높은 동작 주파수의 LLC 공진형 컨버터를 구동하는 경우 낮은 동작 주파수 분해능과 계산 속도에 의해 출력 전압 제어성능과 동특성에 한계가 생긴다. 이를 해결하기 위해 기존의 분해능 및 계산 속도 부족에 의한 영향을 분석하고 Field Programmable Gate Array (FPGA)를 설계하여 높은 동작 주파수 분해능 및 동특성을 얻고자 제안한다. FPGA를 이용한 성능향상을 DSP (TI - TMS 38335)와 FPGA (Xilinx XC7A100T)를 사용하여 비교 분석하고자 한다.