• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.64-67
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• 2005

We fabricated an array consisting of organic TFTs(OTFT) and organic LEDs (OLED) in order to demonstrate the possible application of OTFTs to flexible active matrix OLED (AMOLED). The panel was composed of $64{\times}64$ pixels on 4 inch size polyethylene-terephehalate (PET) substrate in which each pixel had one OTFT integrated with one green OLED. The panel successfully displayed some letters and pictures by emitting green light with a luminance of $1.5\;cd/m^2$ at 6 V, which was controlled by the gate voltage of OTFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.531-534
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• 2005

This paper presents a new data line sharing technique for TFT-LCD panels. This technique reduces the number of data driver IC's to half by having two adjacent pixels share the same data line. This in turn doubles the number of gate lines, which are integrated directly on the glass substrate of amorphous silicon for further cost reduction and more compactness. The proposed technique with new pixel array structure was applied to 15.4 inch WXGA TFT-LCD panels and has proven that the number of driver IC's were halved with nearly 41% circuit cost reduction and 5.3% reduction in power consumption without degrading the image quality.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.130-139
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• 1995

A hierarchical placement system based on routing region assignment has been developed to increase the probability of routing completion after placement. While most of the existing placement systems attempt to reduce the cell density at the portions where routing density is high, our method is distinguished in that specific routing regions are allocated to secure complete routing where the routing density is greater than the routing capacity. Hierarchy is vuilt by clustering and recursive paritioning, and the initial placement obtained by partitioning at each level is improved by using the region refinement algorithm. After placement at each hierarchical level, global routing is performed and fouting regions are assigned, if routing density is greater than routing capacity, to be considered at the next level of placement. the proposed algorithm has been implemented and applied to place several industrical gate-array circuits. A couple of circuits which cannot be routed by using conventional placement techniques can be completely routed by using our new placement technique with routing region assignment.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.363-368
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• 2012

A feedwater controller targeted for an ABWR has been implemented using a modern field programmable gate array (FPGA), and verified using the full scope simulator at Taipower's Lungmen nuclear power station. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulation model of the simulator was employed for verification and validation of the controller design under various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy logic control algorithm is a flexible yet feasible approach for feedwater controller design in nuclear power plant applications.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.129-139
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• 2013

In this paper, we proposed a new hardware architecture for calculating digital holograms at high speed, and verified it with field programmable gate array (FPGA). First, we rearranged memory scheduling and algorithm of computer generated hologram (CGH), and then introduced pipeline technique into CGH process. Finally we proposed a high-performance CGH processor. The hardware was implemented for the target of FPGA, which calculates a unit region of holograms, and it was verified using a hardware environment of NI Inc. and a FPGA of Xilinx Inc. It can generate a hologram of $16{\times}16$ size, and it takes about 4 sec for generating a hologram of a $1,024{\times}1,024$ size, using 6K point sources.

• Bulletin of the Korean Space Science Society
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• 2004.10b
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• pp.293-295
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• 2004

The Engineering Model of on-board computer was developed and tested completely with other sub-systems for STSAT-2. We designed the on-board computer of STSAT-2 which has some improved features compared with that of STSAT-l. A remarkable change is that the on-board computer has a structure of centeralized network communication without a Network Controller of the STSAT-l. That is, the on-board computer directly manages a satellite network. In addition, as many logics are implemented by Field Programmable Gate Array, so we can reduce the weight and size of on-board computer. Also, the developed on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-l.

• Electronics and Telecommunications Trends
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• v.8 no.4
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• pp.186-204
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• 1993

주문형 집적 회로를 설계하기 위한 툴은 여러 종류가 상용화되어 있다. 반도체 연구단 주문형반도체개발센터는 이의 설계를 위하여 최근 콤파스 툴을 설치했다. 콤파스툴은 게이트 어레이와 셀 방식의 주문형 집적 회로를 설계하기 위한 툴로서 가장 보편적인 툴 중의 하나이다. 본 고는 게이트 어레이 방식 주문형 집적회로의 설계 과정을 상세하게 보임으로써 시스템 설계자 (주문형 집적회로 사용자) 에게는 시스템 설계시 고려할 사항을, 주문형 집적회로 설계자에게는 주문형 집적회로 설계를 위한 지침을 제공하고자 작성하였다. 그리고 주문형 집적회로의 설계 과정을 보다 명확하고 실질적으로 파악하기 위하여 각 설계 과정을 콤파스 툴과 연관하여 설명한다. 그러나, 콤파스 툴은 설계과정을 설명하기 위한 도구로만 사용했으므로 툴 자체에 대한 설명은 생략했다.

• Proceedings of the IEEK Conference
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• summer
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• pp.70-73
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• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.533-536
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• 2000

In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.445-446
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• 2006

This paper is concerned with a substantial speed up of image processing methods and less power consumption on 2D images making use of modern FPGA (Field Programmable Gate Array) technology. We implemented 2D FFT and edge detection algorithms based on FPGA and examined processing time and power consumption compared with C/C++ and Alti-Vec technologies.