• Proceedings of the KIEE Conference
• /
• 2000.07a
• /
• pp.215-217
• /
• 2000

Protective relay play a crucial role in the proper operation of a power system, and the reliable transfer of electrical power. This paper deals with the design and implementation of a digital protective relay on a single chip. Implementation on the FPGA(Field Programmable Gate Array) of the chip of digital protective relay. This protective relaying chip monitors the frequency and the voltage and current of the power system. And report the voltage, the current. the frequency, active power and reactive power.

• Proceedings of the KIPE Conference
• /
• 2012.11a
• /
• pp.169-170
• /
• 2012

This paper presents implementation of digital phase controller for thyristor by using FPGA (Field Programmable Gate Array) in HVDC system. Implementation of digital HVDC system is possible by using superior digital simulator such as RTDS (Real Time Digital Simulator). But thyristor phase controller is typically implemented by analog circuit, because it is difficult to implement the phase controller with low operating speed of RTDS. To guarantee high control performance, phase controller needs fast operating speed. This paper presents FPGA based digital phase controller to obtain high speed and high performance. The entire digital simulation of the HVDC system is also implemented by interfacing between FPGA based phase controller and RTDS. Proposed digital HVDC simulator is verified through RTDS simulation.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.93-97
• /
• 2005

This paper proposes a design of stepper motor control in microstep driven mode using FPGA (Field Programmable Gate Array) for hardware implementation. The methods to drive stepper motor in microstep excitation mode are to control of the controlling currents in each phase windings of stepper motor with reference signals. These reference signals are used for controlling the current levels, the required variation of current levels with rotor position can be obtained from the ideal linear or sinusoidal approximations to the static torque-displacement ($T-{\theta}$) characteristic curve. In addition, the hardware implementation of stepper motor controller can be designed uses VHDL (Very high speed integrated circuits Hardware Description Language) and synthesis using an Altera FPGA, FLEX10K family, EPF10K20RC240-4 device as target technology and use MAX+PlusII program for overall development. A multi-stack variable-reluctance stepper motor of Sanyo Denki is used in the experiments.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.97-101
• /
• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.14 no.1
• /
• pp.36-43
• /
• 2015

Optimizing multiple design characteristics which are usually in conflict with each other in the injection molding process is frequently becoming a critical problem for designers who work in this area. The purpose of this work is to develop an automated design methodology for optimizing two such design characteristics found in injection-molded parts. A value function based on decision-making theory is used as a means of evaluating the performance of a two-characteristic design alternative. Also, a design space reduction algorithm based on Taguchi's orthogonal arrays is utilized to discover an optimal design alternative. Verification of the developed design methodology is carried out for an actual model with two design characteristics, the weld line and the gate location, to be optimized in computer simulation experiments.

• Proceedings of the KIPE Conference
• /
• 1999.07a
• /
• pp.274-277
• /
• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• Journal of Power Electronics
• /
• v.10 no.1
• /
• pp.65-71
• /
• 2010

This paper presents the design and implementation of voltage source inverter type SVPWM based speed control of an induction motor using a fuzzy PI controller. This scheme enables us to adjust the speed of the motor by controlling the frequency and amplitude of the stator voltage; the ratio of the stator voltage to the frequency should be kept constant. A model of the fuzzy control system is implemented in real time with a Xilinx FPGA XC3S 400E. It is introduced to maintain a constant speed to when the load varies.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.8C
• /
• pp.812-818
• /
• 2002

반도체 기술과 멀티기디어 통신기술이 발달하면서 고품위의 영상과 다중 채널의 오디오에 관심을 갖게되었다. 특히 DVD 시장의 급성장으로 인하여 고품질의 영상 및 오디오 필요성이 중요한 기술로 대두되었다. MPEG-Audio 표준안은 어떠한 비트율도 지원한다. 본 논문에서는 MPEG-Audio의 핵심부분인 필터부분을 DALUT (Distributed Arithmetic Look-Up Table)방식을 사용하여 FPGA(Field Programmable Gate Array)에 구현하였다. 고속 필터를 설계하기 위해서 승산기 대신에 DALUT를 사용하였으며 최소 10㎒에서 최대 30㎒ 사이에서 동작한다. 본 논문의 설계는 모두 VHDL로 구현하였으며, 알고리즘 검증은 C언어를 사용하였다. VHDL의 시뮬레이션은 ALDEC사의 Active-HDL5.1과 Synopsys사의 vhdlsim을 사용하였고, 합성은 Synopsys사의 design-analyzer를 사용하였다. 타겟 라이브러리는 XILINX사의 XC4010E, XC4020EX, XC4052XL을 사용하였으며, P＆R 툴은 XACT Ml.4를 사용하였다.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.52-55
• /
• 2006

The driving-current degradation of a-Si:H thin-film transistor(TFT) device has been analyzed for the first time. A method to analyze the performance of TFT circuits is presented, which is different from the conventional one by threshold voltage shift method. It can be also used to evaluate the performance of gate driver on array (GOA) circuit, which is integrated in a 12.1" WXGA ($1280{\ast}3{\ast}800$) TFT-LCD panel.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.4C
• /
• pp.379-388
• /
• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.